SLVSH95 July 2024 TPS546C25
ADVANCE INFORMATION
| CMD Address: | 7Eh |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| NVM Back-up: | Yes |
| Updates: | On-the-fly |
The STATUS_CML command returns one data byte with contents relating to communications, logic, and memory as follows. All supported bits may be cleared either by (03h) CLEAR_FAULTS, turning on the output through the mechanism programmed into (02h) ON_OFF_CONFIG, or individually by writing 1b to the STATUS_CML register in their position, per the PMBus 1.3.1 Part II specification section 10.2.3.
Return to Supported PMBus Commands.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W1C | R/W1C | R/W1C | R/W1C | R | R | R/W1C | R |
| IVC | IVD | PEC | MEM | 0 | 0 | OTHER | 0 |
| LEGEND: R/W1C = Read/Write 1 to clear; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7 | IVC | R/W1C | 0b | 0b: Latched flag indicating an invalid or unsupported command was NOT
received. 1b: Latched flag indicating an invalid or unsupported command was received. |
| 6 | IVD | R/W1C | 0b | 0b: Latched flag indicating an invalid or unsupported data was NOT received. 1b: Latched flag indicating an invalid or unsupported data was received. |
| 5 | PEC | R/W1C | 0b | 0b: Latched flag indicating NO packet error check has failed. 1b: Latched flag indicating a packet error check has failed. |
| 4 | MEM | R/W1C | 0b | 0b: Latched flag indicating NO memory error was detected. 1b: Latched flag indicating a memory error was detected. The source of the fault could be one of the following sources internally:
This bit cannot be cleared by any clearing mechanism until the underlying issue is resolved and the memory is updated. |
| 3:2 | Not supported | R | 00b | Not supported and always set to 0. |
| 1 | OTHER | R/W1C | 0b | 0b: Latched flag indicating NO communication error detected. 1b: Latched flag indicating communication error detected. |
| 0 | Not supported | R | 0b | Not supported and always set to 0. |
The corresponding bit (78h) STATUS_BYTE is an OR’ing of the supported bits in this command. When any of the events in this command occurs and the bit representative of the events is set, the corresponding bit in (78h) STATUS_BYTE is updated. Likewise, if this byte is individually cleared (for example, by a write of 1b to a latched condition), it will clear the corresponding bit in (78h) STATUS_BYTE.