SLVSH95 July 2024 TPS546C25
ADVANCE INFORMATION
CMD Address | 09h |
Write Transaction: | Write Block |
Read Transaction: | N/A |
Format: | Unsigned Binary (3 bytes) |
Phased: | No |
NVM Back-up: | No |
Updates: | On-the-fly |
The P2_PLUS_WRITE command is used to send a command and its associated data to:
within the addressed device without altering the value of the PAGE or PHASE command after the P2_PLUS_WRITE command is completed.
The only valid PAGE settings are 00h and FFh, which are treated the same. For any PAGE settings outside the valid range, the primary device will set the IVC bit and assert SMBALERT#. The PHASE setting can be set to the unique phase determined by STACK_POSITION in STACK_CONFIG or all phases (PHASE = FFh). For any PHASE settings outside the valid range, the primary device will set the IVC bit and assert SMBALERT#.
Adds 1 byte to whatever command is being written compared to the P2_PLUS_WRITE
Return to Supported PMBus Commands.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
W | W | W | W | W | W | W | W |
P2_PLUS_WR_CMD | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
W | W | W | W | W | W | W | W |
P2_PLUS_WR_PHASE_NUM | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
W | W | W | W | W | W | W | W |
P2_PLUS_WR_PAGE_NUM |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | Access | Reset | Description |
---|---|---|---|---|
23:16 | P2_PLUS_WR_CMD | W | 00000000b | |
15:8 | P2_PLUS_WR_PHASE_NUM | W | 00000000b | |
7:0 | P2_PLUS_WR_PAGE_NUM | W | 00000000b |