SLVSH95 July 2024 TPS546C25
ADVANCE INFORMATION
CMD Address | 61h |
Write Transaction: | Write Word |
Read Transaction: | Read Word |
Format: | LINEAR11 |
NVM Backup: | EEPROM or Pin Detection |
Updates: | On-the-fly |
The TON_RISE command sets the time, in milliseconds, from when the output starts to rise until the voltage has entered the regulation band, which effectively sets the slew rate of the reference DAC during the soft-start period. The soft-start time varies from the TON_RISE selection when VOUT_COMMAND is used for boot up. See section Startup for more details.
Return to Supported PMBus Commands.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
R | R | R | R | R | R | R | R |
EXPONENT | TON_RISE | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R | R | RW | RW | RW | RW | RW | RW |
TON_RISE |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | Access | Reset | Description |
---|---|---|---|---|
15:11 | EXPONENT | R | 11111b | Linear format two’s complement exponent. The exponent is not programmable, with a result of 0.5ms LSB. |
10:6 | Reserved | R | 00000b | Not used and always set to 0. |
5:0 | TON_RISE | R/W | 000000b | These bits select the TON_RISE time. |
Every mantissa binary value in the writable bits is writeable and readable. However, the actual divider is set to the nearest supported value. Additionally, that mantissa value restored from EEPROM is fixed for each setting supported in hardware.
Attempts to change the read-only bits (TON_RISE[15:6]) will be considered invalid/unsupported data. The device will NACK the unsupported data and the received value will be ignored. The ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the (7Eh) STATUS_CML registers will be set.
TON_RISE [5:0] | TON_RISE (ms) | |
---|---|---|
Greater than or equal to | Less than | |
2d | 0.5 | |
2d | 4d | 1 |
4d | 8d | 2 |
8d | 16d | 4 |
16d | 32d | 8 |
32d | 64d | 16 |