The TPS55340-EP requires external compensation which allows the loop response to be optimized for each application. The COMP pin is the output of the internal error amplifier. An external resistor, R3, and ceramic capacitor, C4, are connected to the COMP pin to provide a pole and a zero, shown in Figure 9-1. This pole and zero, along with the inherent pole and zero of a boost converter, determine the closed-loop frequency response. This is important for converter stability and transient response. Loop compensation should be designed for the minimum operating voltage.

The following equations summarize the loop equations for the TPS55340-EP configured as a CCM boost converter. They include the power stage output pole (ƒ_OUT) and the right-half-plane zero (ƒ_RHPZ) of a boost converter calculated with Equation 27 and Equation 28 respectively. When calculating ƒ_OUT, it is important to include the derating of ceramic output capacitors. In the example with an estimated 10.2-µF capacitance, these frequencies are calculated to 980 and 22.1 kHz respectively. The DC gain (A) of the power stage is calculated with Equation 27 and is 39.9 dB in this design. The compensation pole (ƒ_P) and zero (ƒ_Z) generated by R3, C4, and internal transconductance amplifier are calculated with Equation 30 and Equation 31, respectively.

Most CCM boost converters have a stable control loop if f_Z is set slightly above ƒ_P through proper sizing of R3 and C4. A good starting point is C4 = 0.1 µF and R3 = 2 kΩ. Increasing R3 or reducing C4 increases the closed-loop bandwidth, and therefore improves the transient response. Adjusting R3 and C4 in opposite directions increases the phase and gain margin of the loop, which improves loop stability. TI generally recommends to limit the bandwidth of the loop to the lower of either 1/5 of the switching frequency ƒ_SW or 1/3 the RHPZ frequency, ƒ_RHPZ, shown in Equation 28. The spreadsheet tool located in the TPS55340-EP product folder can also be used to aid in compensation design.

Equation 27.

Equation 28.

Equation 29.

Equation 30.

Equation 31.

Equation 32.

Equation 33.

where

• C_OUT is the equivalent output capacitor (C_OUT = C8 + C9 + C10)
• R_OUT is the equivalent load resistance (V_OUT / I_OUT)
• Gea is the error amplifier transconductance located in the Section 7.5
• R_SENSE (15 mΩ, typical) is the sense resistor in the current control loop
• ƒ_co1 and ƒ_co2 are possible bandwidth.

An additional capacitor from the COMP pin to GND (C5) can be used to place a high-frequency pole in the control loop. This is not always necessary with ceramic output capacitors. If a non-ceramic output capacitor is used, there is an additional zero (ƒ_ZESR) in the control loop which can be calculated with Equation 35. The value of C5 and the pole created by C5 can be calculated with Equation 36 and Equation 34, respectively. Finally, if more phase margin is needed, an additional zero (ƒ_ZFF) can be added by placing a capacitor (C_FF) in parallel with the top feedback resistor R1. TI recommends to place the zero at the target crossover frequency or higher. The feed forward capacitor also adds a pole at a higher frequency. Calculate the recommended value of C_FF with Equation 37.

Equation 34.

Equation 35.

Equation 36.

Equation 37.

where

• R_ESR is the ESR of the output capacitor

If a network measurement tool is available, the most accurate compensation design can be achieved following this procedure. The power stage frequency response is first measured using a network analyzer at the minimum 5-V input and maximum 800-mA load. This measurement is shown in Figure 9-2. In this design, only one pole and one zero are used, so the maximum phase increase from the compensation will be 180°. For a 60° phase margin, the power stage phase must be –120° at its lowest point. Based on the target 6-kHz bandwidth, the measured power stage gain, K_PS(ƒ_BW), is 24.84 dB and the phase is –110.3°.

Figure 9-2 Power Stage Gain and Phase of the Boost Converter

R3 is then chosen to set the compensation gain to be the reciprocal of the power stage gain at the target bandwidth using Equation 38. C4 is then chosen to place a zero at 1/10 the target bandwidth with Equation 39. In this case, R3 is calculated to be 2.56 kΩ, the nearest standard value 2.55 kΩ is used. C4 is calculated at
0.104 µF and the nearest standard value 0.100 µF is used. Although not necessary because this design uses all ceramic capacitors, a 100-pF capacitor is selected for C5 to add a high-frequency pole at a frequency 100× the target bandwidth.

Equation 38.

Equation 39.