ZHCSCL9A July 2014 – September 2021 TPS55340-EP
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 说明（续）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Switching Frequency
- 8.3.2 Voltage Reference and Setting Output Voltage
- 8.3.3 Soft Start
- 8.3.4 Slope Compensation
- 8.3.5 Overcurrent Protection and Frequency Foldback
- 8.3.6 Enable and Thermal Shutdown
- 8.3.7 Undervoltage Lockout (UVLO)
- 8.3.8 Minimum On-Time and Pulse Skipping
- 8.3.9 Layout Considerations
- 8.3.10 Thermal Considerations
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Applications
- 9.2.1
Boost Converter Application
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 Selecting the Switching Frequency (R4)
- 9.2.1.2.2 Determining the Duty Cycle
- 9.2.1.2.3 Selecting the Inductor (L1)
- 9.2.1.2.4 Computing the Maximum Output Current
- 9.2.1.2.5 Selecting the Output Capacitor (C8 to C10)
- 9.2.1.2.6 Selecting the Input Capacitors (C2, C7)
- 9.2.1.2.7 Setting Output Voltage (R1, R2)
- 9.2.1.2.8 Setting the Soft-Start Time (C7)
- 9.2.1.2.9 Selecting the Schottky Diode (D1)
- 9.2.1.2.10 Compensating the Control Loop (R3, C4, C5)
- 9.2.1.3 Application Curves
- 9.2.2
SEPIC Converter Application
- 9.2.2.1 Design Requirements
- 9.2.2.2
Detailed Design Procedure
- 9.2.2.2.1 Selecting the Switching Frequency (R4)
- 9.2.2.2.2 Duty Cycle
- 9.2.2.2.3 Selecting the Inductor (L1)
- 9.2.2.2.4 Calculating the Maximum Output Current
- 9.2.2.2.5 Selecting the Output Capacitor (C8 to C10)
- 9.2.2.2.6 Selecting the Series Capacitor (C6)
- 9.2.2.2.7 Selecting the Input Capacitor (C2, C7)
- 9.2.2.2.8 Selecting the Schottky Diode (D1)
- 9.2.2.2.9 Setting the Output Voltage (R1, R2)
- 9.2.2.2.10 Setting the Soft-Start Time (C3)
- 9.2.2.2.11 MOSFET Rating Considerations
- 9.2.2.2.12 Compensating the Control Loop (R3, C4)
- 9.2.2.3 SEPIC Converter Application Curves
- 9.2.1
Boost Converter Application
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
9.2.2.2.12 Compensating the Control Loop (R3, C4)
This design was compensated by measuring the frequency response of the power stage at the lowest input voltage of 6 V and choosing the components for the desired bandwidth. The lowest right half plane zero (ƒRHPZ) is calculated to be 36.7 kHz with Equation 52. Using the recommendation to limit the bandwidth to 1/3 of ƒRHPZ, the maximum recommended is 12.2 kHz.
This design also uses only one pole and one zero. To achieve approximately 60° of phase margin, the power stage phase must be no lower than approximately –120° at the desired bandwidth. To ensure a stable design, R3 was initially set to 1 kΩ and C4 was 1 µF. Figure 9-11 shows the measurement of the power stage At 7 kHz, the power stage has a gain of 19.52 dB and phase of –118.1°.
Figure 9-11 SEPIC Power Stage Gain and PhaseAs there are no changes in the transconductance amplifier, the equations used to calculate the external compensation components in a boost design can be used in the SEPIC design. Using the maximum Gea from the electrical specification of 440 µmho, Equation 38 calculates the nearest standard value of R3 to be 2.37 kΩ. Using Equation 39, C4 is calculated to the nearest standard value of 0.1 µF.