7.4.1 Sequencing

Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of another device. The sequential method is illustrated in Figure 42 using two TPS57060-Q1 devices. The power good is coupled to the EN pin on the TPS57060-Q1 device which enables the second power supply when the primary supply reaches regulation. If needed, a 1nF ceramic capacitor on the EN pin of the second power supply provides a 1-ms start-up delay. Figure 43 shows the results of Figure 42.

Figure 44 shows a method for ratiometric start-up sequence by connecting the SS/TR pins together. The regulator outputs will ramp up and reach regulation at the same time. When calculating the slow start time the pullup current source must be doubled in Equation 6. Figure 45 shows the results of Figure 44.

Figure 42. Schematic for Sequential Start-Up Sequence

Figure 43. Sequential Startup Using EN and PWRGD

Figure 44. Schematic for Ratiometric Start-Up Using Coupled SS/TR Pins

Figure 45. Ratiometric Startup Using Coupled SS/TR pins

Figure 46. Schematic for Ratiometric and Simultaneous Start-Up Sequence

Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 46 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 24 and Equation 25, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1. Equation 26 is the voltage difference between Vout1 and Vout2 at the 95% of nominal output regulation.

The deltaV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and tracking resistors, the Vssoffset and Iss are included as variables in the equations.

To design a ratiometric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 24 through Equation 26 for deltaV. Equation 26 results in a positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved.

Because the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO or thermal shutdown fault, careful selection of the tracking resistors is needed to ensure the device will restart after a fault. Make sure the calculated R1 value from Equation 24 is greater than the value calculated in Equation 27 to ensure the device can recover from a fault.

As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage needs to be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in Figure 23.

Equation 24.

Equation 25.

Equation 26.

Equation 27.

Figure 47. Ratiometric Startup With VOUT2 Leading VOUT1

Figure 49. Simultaneous Startup With Tracking Resistor

Figure 48. Ratiometric Startup With VOUT1 Leading VOUT2