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ZHCSD50D December 2014 – February 2017 TPS62170-Q1 , TPS62171-Q1 , TPS62172-Q1

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DSG|8
- MPDS308C

散热焊盘机械数据 (封装 | 引脚)

DSG|8
- QFND141I

订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Pin voltage⁽²⁾	VIN	–0.3	20	V
	EN	–0.3	V_IN+0.3	V
	SW	-0.3	V_IN+0.3	V
	FB, PG, VOS	–0.3	7	V
Power Good sink current	PG		10	mA
Operating junction temperature range, T_J		–40	150	°C
Storage temperature range, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to network ground terminal.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002⁽¹⁾		±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per AEC Q100-011		±500	V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Supply voltage	3	17	V
V_OUT	Output voltage range	0.9	6	V
T_J	Operating junction temperature	–40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS6217x-Q1	UNIT
THERMAL METRIC⁽¹⁾		DSG (8 PINS)	UNIT
R_θJA	Junction-to-ambient thermal resistance	65.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	66.4	°C/W
R_θJB	Junction-to-board thermal resistance	35.5	°C/W
ψ_JT	Junction-to-top characterization parameter	1.7	°C/W
ψ_JB	Junction-to-board characterization parameter	35.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	8.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, .

7.5 Electrical Characteristics

over junction temperature range (T_J = –40°C to +125°C), typical values at V_IN = 12 V and T_J = 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY
V_IN	Input voltage range⁽¹⁾		3		17	V
I_Q	Operating quiescent current	EN = High, IOUT = 0 mA, Device not switching		17	30	µA
I_SD	Shutdown current⁽²⁾	EN = Low		1.8	25	µA
V_UVLO	Undervoltage lockout threshold	Falling input voltage	2.6	2.7	2.82	V
V_UVLO	Undervoltage lockout threshold	Hysteresis		180		mV
T_SD	Thermal shutdown temperature			160		°C
T_SD	Thermal shutdown hysteresis			20		°C
CONTROL (EN, PG)
V_{EN_H}	High-level input threshold voltage (EN)		0.9			V
V_{EN_L}	Low-level input threshold voltage (EN)				0.3	V
I_{LKG_EN}	Input leakage current (EN)	EN = V_IN or GND		0.01	1	µA
V_{TH_PG}	Power Good threshold voltage	Rising (%V_OUT)	92%	95%	98%
V_{TH_PG}	Power Good threshold voltage	Falling (%V_OUT)	87%	90%	93%
V_{OL_PG}	Power Good output low	I_PG = –2 mA		0.07	0.3	V
I_{LKG_PG}	Input leakage current (PG)	V_PG = 1.8 V		1	400	nA
POWER SWITCH
R_DS(ON)	High-side MOSFET ON-resistance	V_IN ≥ 6 V		300	600	mΩ
	High-side MOSFET ON-resistance	V_IN = 3 V		430		mΩ
	Low-side MOSFET ON-resistance	V_IN ≥ 6 V		120	200	mΩ
	Low-side MOSFET ON-resistance	V_IN = 3 V		165		mΩ
I_LIMF	High-side MOSFET forward current limit⁽³⁾	V_IN = 12 V, T_A = 25°C	0.85	1.05	1.35	A
OUTPUT
VREF	Internal reference voltage			0.8		V
I_{LKG_FB}	Pin leakage current (FB)	TPS62170-Q1, V_FB = 1.2 V		5	400	nA
V_OUT	Output voltage range	TPS62170-Q1, V_IN ≥ V_OUT	0.9		6.0	V
	Feedback voltage accuracy⁽⁴⁾	PWM Mode operation, V_IN ≥ V_OUT + 1 V	–3%		3%
	Feedback voltage accuracy⁽⁴⁾	Power Save Mode operation, C_OUT = 22 µF⁽⁵⁾	–3.5%		4%
	DC output voltage load regulation⁽⁶⁾	V_IN = 12 V, V_OUT = 3.3 V, PWM Mode operation		0.05		% / A
	DC output voltage line regulation ⁽⁶⁾	3 V ≤ V_IN ≤ 17 V, V_OUT = 3.3 V, I_OUT = 0.5 A, PWM Mode operation		0.02		% / V

(1) The device is still functional down to Under Voltage Lockout (see parameter V_UVLO).

(2) Current into VIN pin.

(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit and Short Circuit Protection).

(4) For fixed voltage versions, the (internal) resistive feedback divider is included.

(5) The accuracy in Power Save Mode can be improved by increasing the C_OUT value, reducing the output voltage ripple.

(6) Line and load regulation are depending on external component selection and layout (see Figure 14 and Figure 15).

7.6 Typical Characteristics

At V_IN = 12 V, V_OUT = 3.3 V and T_J = 25°C (unless otherwise noted)

TPS62170-Q1 TPS62171-Q1 TPS62172-Q1 SLVSCK6_IQ.gif

Figure 1. Quiescent Current

TPS62170-Q1 TPS62171-Q1 TPS62172-Q1 SLVSCK6_RDSonHS.gif

Figure 3. High-Side Static Drain-Source-Resistance (R_DSon)

TPS62170-Q1 TPS62171-Q1 TPS62172-Q1 SLVSCK6_ISD.gif

Figure 2. Shutdown Current

TPS62170-Q1 TPS62171-Q1 TPS62172-Q1 SLVSCK6_RDSonLS.gif

Figure 4. Low-Side Static Drain-Source-Resistance (R_DSon)