The TPS6244x-Q1 synchronous dual switch mode power converters are based on a peak current mode control topology. The control loop is internally compensated. To optimize the bandwidth of the control loop to the wide range of output capacitance that can be used with TPS6244x-Q1, the internal compensation has two settings. See Section 9.3.2. One out of the two compensation settings is chosen either by a resistor from COMP/FSET to GND, or by the logic state of this pin. The regulation network achieves fast and stable operation with small external components and low-ESR ceramic output capacitors. The devices can be operated without a feedforward capacitor on the output voltage divider, however, using a typically 10-pF feedforward capacitor improves transient response.

The devices support forced fixed-frequency PWM operation with the MODE pin tied to a logic high level. The frequency is defined as either 2.25 MHz internally fixed when COMP/FSET is tied to GND or VIN or in a range of 1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices can be synchronized to an external clock signal in a range from 2 MHz to 4 MHz, applied to the MODE pin with no need for additional passive components. External synchronization can only be used when there is a resistor from COMP/FSET to GND. When COMP/FSET is directly tied to GND or VIN, the TPS6244x-Q1 cannot be synchronized externally. The TPS6244x-Q1 allows for a change from internal clock to external clock during operation. When the MODE pin is set to a logic low level, the device operates in power save mode (PFM) at low output current and automatically transfers to fixed frequency PWM mode at higher output current. In PFM mode, the switching frequency decreases linearly based on the load to sustain high efficiency down to very low output current. When a converter switches from PFM to PWM operation, there can be a maximum delay of one clock cycle because in this case, the converter has to synchronize to the other converter to achieve 180 degrees phase shift.