TPS650860 Configurable Multirail PMU for Multicore Processors
- SWCS128A March 2015 – December 2015
  
  PRODUCTION DATA.

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DATA SHEET

TPS650860 Configurable Multirail PMU for Multicore Processors

1 Device Overview

1.1 Features

Wide V_IN Range From 5.6 V to 21 V
Three Variable-Output Voltage Synchronous
Step-Down Controllers With DCAP2™ Topology
- Scalable Output Current Using External FETs With Selectable Current Limit
- I²C DVS Control From 0.41 V to 1.67 V in 10-mV Steps or 1 V to 3.575 V in 25-mV Steps
Three Variable-Output Voltage Synchronous Step-Down Converters With DCS-Control Topology
- V_IN Range From 4.5 V to 5.5 V
- Up to 3 A of Output Current
- I²C DVS Control From 0.41 V to 1.67 V in 10-mV Steps or 0.425 V to 3.575 V in 25-mV Steps
Three LDO Regulators With Adjustable Output Voltage
- LDOA1: I²C-Selectable Output Voltage From 1.35 V to 3.3 V for up to 200 mA of Output Current
- LDOA2 and LDOA3: I²C-Selectable Output Voltage From 0.7 V to 1.5 V for up to 600 mA of Output Current
VTT LDO for DDR Memory Termination
Three Load Switches With Slew Rate Control
- Up to 300 mA of Output Current With Voltage Drop Less Than 1.5% of Nominal Input Voltage
- R_DSON < 96 mΩ at Input Voltage of 1.8 V
5-V Fixed-Output Voltage LDO (LDO5)
- Power Supply for Gate Drivers of SMPS and for LDOA1
- Automatic Switch to External 5-V Buck for Higher Efficiency
Built-in Flexibility and Configurability by Factory OTP Programming
- Six GPI Pins Configurable to Enable (CTL1 to CTL6) or Sleep Mode Entry (CTL3 and CTL6) of Any Selected Rails
- Four GPO Pins Configurable to Power Good of Any Selected Rails
- Open-Drain Interrupt Output Pin
I²C Interface Supports:
- Standard Mode (100 kHz)
- Fast Mode (400 kHz)
- Fast Mode Plus (1 MHz)

1.2 Applications

Residential Gateway
POS Terminals
Test and Measurement
Programmable Logic Controllers
Embedded PCs
Human to Machine Interfaces

1.3 Description

The TPS650860 device is a single-chip power-management IC designed for multicore processors, FPGAs, and other System-on-Chips (SoCs). The TPS650860 offers an input range of 5.6 V to 21 V, enabling a wide range of applications. The device is well suited for NVDC and non-NVDC power architecture using 2S, 3S, or 4S Li-Ion battery packs. See the Application Section for 5-V input supplies. The D-CAP2™ and DCS-Control high-frequency voltage regulators use small inductors and capacitors to achieve a small solution size. The D-CAP2 and DCS-Control topologies have excellent transient response performance, which is great for processor core and system memory rails that have fast load switching. An I²C interface allows simple control either by an embedded controller (EC) or by an SoC. The PMIC comes in an
8-mm × 8-mm, single-row VQFN package with thermal pad for good thermal dissipation and ease of board routing.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS650860	VQFN (64)	8.00 mm × 8.00 mm

(1) For more information, see the Mechanical Packaging and Orderable Information section.

1.4 Functional Block Diagram

Figure 1-1 PMIC Functional Block Diagram

2 Revision History

Changes from * Revision (March 2015) to A Revision

Changed device status from: PRODUCT PREVIEW to: PRODUCTION DATA Go

3 Pin Configuration and Functions

The thermal pad must be connected to the system power ground plane.

Figure 3-1 RSK (VQFN) Pin Map Diagram

Pin Functions

NO.	NAME	I/O	DESCRIPTION
SMPS REGULATORS
1	FBGND2	I	Remote negative feedback sense for BUCK2 controller. Connect to negative terminal of output capacitor.
2	FBVOUT2	I	Remote positive feedback sense for BUCK2 controller. Connect to positive terminal of output capacitor.
3	DRVH2	O	High-side gate driver output for BUCK2 controller.
4	SW2	I	Switch node connection for BUCK2 controller.
5	BOOT2	I	Bootstrap pin for BUCK2 controller. Connect a 100-nF ceramic capacitor between this pin and SW2 pin.
6	PGNDSNS2	I	Power GND connection for BUCK2. Connect to ground terminal of external low-side FET.
7	DRVL2	O	Low-side gate driver output for BUCK2 controller.
8	DRV5V_2_A1	I	5-V supply to BUCK2 gate driver and LDOA1. Bypass to ground with a 2.2-µF (TYP) ceramic capacitor. Shorted on board to LDO5P0 pin typically.
10	LX3	O	Switch node connection for BUCK3 converter.
11	PVIN3	I	Power input to BUCK3 converter. Bypass to ground with a 10-µF (TYP) ceramic capacitor.
12	FB3	I	Remote feedback sense for BUCK3 converter. Connect to positive terminal of output capacitor.
20	LX5	O	Switch node connection for BUCK5 converter.
21	PVIN5	I	Power input to BUCK5 converter. Bypass to ground with a 10-µF (TYP) ceramic capacitor.
22	FB5	I	Remote feedback sense for BUCK5 converter. Connect to positive terminal of output capacitor.
23	FB4	I	Remote feedback sense for BUCK4 converter. Connect to positive terminal of output capacitor.
24	PVIN4	I	Power input to BUCK4 converter. Bypass to ground with a 10-µF (TYP) ceramic capacitor.
25	LX4	O	Switch node connection for BUCK4 converter.
29	FBVOUT1	I	Remote feedback sense for BUCK1 controller. Connect to positive terminal of output capacitor.
30	ILIM1	I	Current limit set pin for BUCK1 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET.
33	DRVH1	O	High-side gate driver output for BUCK1 controller.
34	SW1	I	Switch node connection for BUCK1 controller.
35	BOOT1	I	Bootstrap pin for BUCK1 controller. Connect a 100-nF ceramic capacitor between this pin and SW1 pin.
36	PGNDSNS1	I	Power GND connection for BUCK1. Connect to ground terminal of external low-side FET.
37	DRVL1	O	Low-side gate driver output for BUCK1 controller.
38	DRV5V_1_6	I	5-V supply to BUCK1 and BUCK6 gate drivers. Bypass to ground with a 2.2-µF (TYP) ceramic capacitor. Shorted on board to LDO5P0 pin typically.
39	DRVL6	O	Low-side gate driver output for BUCK6 controller.
40	PGNDSNS6	I	Power GND connection for BUCK6. Connect to ground terminal of external low-side FET.
41	BOOT6	I	Bootstrap pin for BUCK6 controller. Connect a 100-nF ceramic capacitor between this pin and SW6 pin.
42	SW6	I	Switch node connection for BUCK6 controller.
SMPS REGULATORS (continued)
43	DRVH6	O	High-side gate driver output for BUCK6 controller.
44	FBVOUT6	I	Remote feedback sense for BUCK6 controller. Connect to positive terminal of output capacitor.
45	ILIM6	I	Current limit set pin for BUCK6 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET.
64	ILIM2	I	Current limit set pin for BUCK2 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET.
LDO and LOAD SWITCHES
9	LDOA1	O	LDOA1 output. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor. Leave floating when not in use.
17	SWB1	O	Output of load switch B1. Bypass to ground with a 0.1-µF (TYP) ceramic capacitor. Leave floating when not in use.
18	PVINSWB1_B2	I	Power supply to load switch B1 and B2. Bypass to ground with a 1-µF (TYP) ceramic capacitor to improve transient performance. Connect to ground when not in use.
19	SWB2	O	Output of load switch B2. Bypass to ground with a 0.1-µF (TYP) ceramic capacitor. Leave floating when not in use.
31	SWA1	O	Output of load switch A1. Bypass to ground with a 0.1-µF (TYP) ceramic capacitor. Leave floating when not in use.
32	PVINSWA1	I	Power supply to load switch A1. Bypass to ground with a 1-µF (TYP) ceramic capacitor to improve transient performance. Connect to ground when not in use.
46	PVINVTT	I	Power supply to VTT LDO. Bypass to ground with a 10-µF (MIN) ceramic capacitor.
47	VTT	O	Output of load VTT LDO. Bypass to ground with 2× 22-µF (MIN) ceramic capacitors.
48	VTTFB	I	Remote feedback sense for VTT LDO. Connect to positive terminal of output capacitor.
49	LDOA3	O	Output of LDOA3. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor. Leave floating when not in use.
50	PVINLDOA2_A3	I	Power supply to LDOA2 and LDOA3. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor. Connect to ground when not in use.
51	LDOA2	O	Output of LDOA2. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor. Leave floating when not in use.
54	LDO3P3	O	Output of 3.3-V internal LDO. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor.
56	LDO5P0	O	Output of 5-V internal LDO or an internal switch that connects this pin to V5ANA. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor.
57	V5ANA	I	External 5-V supply input to internal load switch that connects this pin to LDO5P0 pin. Bypass this pin with an optional ceramic capacitor to improve transient performance.
INTERFACE
13	CTL1	I	Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
14	CTL6/SLPENB2	I	Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin. Alternatively, when configured to active-low sleep enable, a group of VRs chosen can be entered into (L) or out of (H) sleep state where their output voltages may be different from those in normal state.
15	IRQB	O	Open-drain output interrupt pin. Refer to Section 5.9.3 for definitions.
16	GPO1	O	General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the configuration, the pin can be programmed either to reflect power good status of VRs of any choice or to be controlled by an I²C register bit by the user, which then can be used as an enable signal to an external VR.
26	GPO2	O	General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the configuration, the pin can be programmed either to reflect power good status of VRs of any choice or to be controlled by an I²C register bit by the user, which then can be used as an enable signal to an external VR.
27	GPO3	O	General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the configuration, the pin can be programmed either to reflect power good status of VRs of any choice or to be controlled by an I²C register bit by the user, which then can be used as an enable signal to an external VR.
28	GPO4	O	Open-drain output that can be configured to reflect power good status of VRs of any choice or to be controlled by an I²C register bit by the user, which then can be used as an enable signal to an external VR.
58	CLK	I	I²C clock
59	DATA	I/O	I²C data
60	CTL2	I	Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
61	CTL3/SLPENB1	I	Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin. Alternatively, when configured to active-low sleep enable, a group of VRs chosen can be entered into (L) or out of (H) sleep state where their output voltages may be different from those in normal state.
62	CTL4	I	Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
63	CTL5	I	Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
REFERENCE
53	VREF	O	Band-gap reference output. Stabilize it by connecting a 100-nF (TYP) ceramic capacitor between this pin and quiet ground.
52	AGND	—	Analog ground. Do not connect to the thermal pad ground on top layer. Connect to ground of VREF capacitor.
55	VSYS	I	System voltage detection and input to internal LDOs (3.3 V and 5 V). Bypass to ground with a 1-µF (TYP) ceramic capacitor.
THERMAL PAD
Thermal pad		—	Connect to PCB ground plane using multiple vias for good thermal and electrical performance.

4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
ANALOG
VSYS	Input voltage from battery	–0.3	28	V
PVIN3, PVIN4, PVIN5, LDO5P0, DRV5V_1_6, DRV5V_2_A1, DRVL1, DRVL2, DRVL6		–0.3	7	V
V5ANA		–0.3	6	V
PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2		–0.3	0.3	V
DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6		–0.3	34	V
SW1, SW2, SW6		–2⁽²⁾	28	V
LX3, LX4, LX5		–1⁽³⁾	7	V
BOOTx to SWx	Differential voltage	–0.3	5.5	V
VREF, LDO3P3, FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5, ILIM1, ILIM2, ILIM6, PVINVTT, VTT, VTTFB, PVINSWA1, SWA1, PVINSWB1_B2, SWB1, SWB2, LDOA1		–0.3	3.6	V
PVINLDOA2_A3, LDOA2, LDOA3		–0.3	3.3	V
DIGITAL IOs
DATA, CLK, GPO1-GPO3		–0.3	3.6	V
CTL1-CTL6, GPO4, IRQB		–0.3	7	V
T_stg	Storage temperature	–40	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Transient for less than 5 ns.

(3) Transient for less than 20 ns.

4.2 ESD Ratings

				VALUE	UNIT
V_ESD	Electrostatic discharge (ESD) performance	Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001⁽¹⁾		±1000	V
V_ESD	Electrostatic discharge (ESD) performance	Charged Device Model (CDM), per JESD22-C101⁽²⁾	All pins	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
ANALOG
VSYS		5.6	13	21	V
VREF		–0.3		1.3	V
PVIN3, PVIN4, PVIN5, LDO5P0, V5ANA, DRV5V_1_6, DRV5V_2_A1		–0.3	5	5.5	V
PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2		–0.3		0.3	V
DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6		–0.3		26.5	v
DRVL1, DRVL2, DRVL6		–0.3		5.5	V
SW1, SW2, SW6		–1		21	V
LX3, LX4, LX5		–1		5.5	V
FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5		–0.3		3.6	V
LDO3P3, ILIM1, ILIM2, ILIM6, LDOA1		–0.3		3.3	V
PVINVTT		–0.3	1.2 / 1.35	FBVOUT6	V
VTT, VTTFB		–0.3		FBVOUT6 / 2	V
PVINSWA1, SWA1		–0.3	3.3	3.6	V
PVINSWB1_B2, PVINLDOA2_A3, SWB1, SWB2		–0.3		1.8	V
LDOA2, LDOA3		–0.3		1.5	V
DIGITAL IOs
DATA, CLK, CTL1–CTL6, GPO1–GPO4, IRQB		–0.3		3.3	V
CHIP
T_A	Operating ambient temperature range	–40	27	85	°C
T_J	Operating junction temperature range	–40	27	125	°C

4.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS650860	UNIT
		RSK (VQFN)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance	25.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	11.3	°C/W
R_θJB	Junction-to-board thermal resistance	4.4	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	4.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

4.5 Electrical Characteristics: Total Current Consumption

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A = 25°C) (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_SD	PMIC shutdown current that includes I_Q for References, LDO5, LDO3P3, and digital core	V_SYS = 13 V, all functional output rails are disabled		65		µA

4.6 Electrical Characteristics: Reference and Monitoring System

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A = 25°C) (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
REFERENCE
V_REF	Bandgap reference Voltage			1.25		V
V_REF	Accuracy		–0.5%		0.5%
C_VREF	Bandgap output capacitor		0.047	0.1	0.22	µF
V_{SYS_UVLO_5V}	VSYS UVLO threshold for LDO5	V_SYSfalling	5.24	5.4	5.56	V
V_{SYS_UVLO_5V_HYS}	VSYS UVLO threshold hysteresis for LDO5	V_SYS rising above V_{SYS_UVLO_5V}		200		mV
V_{SYS_UVLO_3V}	VSYS UVLO threshold for LDO3P3	V_SYS falling	3.45	3.6	3.75	V
V_{SYS_UVLO_3V_HYS}	VSYS UVLO threshold hysteresis for LDO3P3	V_SYS rising above V_{SYS_UVLO_3V}		150		mV
T_CRIT	Critical threshold of die temperature	T_J rising	130	145	160	°C
T_{CRIT_HYS}	Hysteresis of T_CRIT	T_J falling		10		°C
T_HOT	Hot threshold of die temperature	T_J rising	110	115	120	°C
T_{HOT_HYS}	Hysteresis of T_HOT	T_J falling		10		°C
LDO5
V_IN	Input voltage at V_SYS pin		5.6	13	21	V
V_OUT	DC output voltage	I_OUT = 10 mA	4.9	5	5.1	V
I_OUT	DC output current			100	180	mA
I_OCP	Overcurrent protection	Measured with output shorted to ground	200			mA
V_{TH_PG}	Power Good assertion threshold in percentage of target V_OUT	V_OUT rising		94%
V_{TH_PG_HYS}	Power Good deassertion hysteresis	V_OUT rising or falling		4%
I_Q	Quiescent current	V_IN = 13 V, I_OUT = 0 A		20		µA
C_OUT	External output capacitance		2.7	4.7	10	µF
V5ANA-to-LDO5P0 LOAD SWITCH
R_DSON	On resistance	V_IN = 5 V, measured from V5ANA pin to LDO5P0 pin at I_OUT = 200 mA			1	Ω
V_{TH_PG}	Power Good threshold for external 5-V supply	V_V5ANA rising		4.7		V
V_{TH_HYS_PG}	Power Good threshold hysteresis for external 5-V supply	V_V5ANA falling		100		mV
I_LKG	Leakage current	Switch disabled, V_V5ANA = 5 V, V_LDO5 = 0 V			10	µA
LDO3P3
V_IN	Input voltage at V_SYS pin		5.6	13	21	V
V_OUT	DC output voltage	I_OUT = 10 mA		3.3		V
V_OUT	Accuracy	V_IN = 13 V, I_OUT = 10 mA	–3%		3%
I_OUT	DC output current				40	mA
I_OCP	Overcurrent protection	Measured with output shorted to ground	70			mA
V_{TH_PG}	Power Good assertion threshold in percentage of target V_OUT	V_OUT rising		92%
V_{TH_PG_HYS}	Power Good deassertion hysteresis	V_OUT falling		3%
I_Q	Quiescent current	V_IN = 13 V, I_OUT = 0 A		20		µA
C_OUT	External output capacitance		2.2	4.7	10	µF

4.7 Electrical Characteristics: Buck Controllers

over recommended input voltage range, T_A = –40°C to 85°C and T_A = 25°C for typical values (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
BUCK1, BUCK2, BUCK6
V_IN	Power input voltage for external HSD FET		5.6	13	21	V
V_OUT	DC output voltage VID range and options	VID step size = 10 mV, BUCKx_VID[6:0] progresses from 0000001 to 1111111	0.41		1.67	V
	DC output voltage VID range and options	VID step size = 25 mV, BUCKx_VID[6:0] progresses from 0000001 to 1111111	1⁽¹⁾		3.575	V
	BUCK1 output voltage	Set by BUCK1_VID[6:0], 10 mV step size selected		1.05		V
	BUCK2 output voltage	Set by BUCK2_VID[6:0], 25 mV step size selected		3.3		V
	BUCK6 output voltage	Set by BUCK6_VID[6:0], 10 mV step size selected		1.5		V
	DC output voltage accuracy	V_OUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, I_OUT = 100 mA to 7 A	–2%		2%
	Total output voltage accuracy (DC + ripple) in DCM	I_OUT = 10 mA, V_OUT ≤ 1 V	–30		40	mV
SR(V_OUT)	Output DVS slew rate		2.5	3.125		mV/µs
I_{LIM_LSD}	Low-side output valley current limit accuracy (programmed by external resistor R_LIM)		–15%		15%
I_LIMREF	Source current out of ILIM1 pin	T = 25°C	45	50	55	µA
V_LIM	Voltage at ILIM1 pin	V_LIM = R_LIM × I_LIMREF	0.2		2.25	V
ΔV_OUT/ΔV_IN	Line regulation	V_OUT= 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, I_OUT = 7 A	–0.5%		0.5%
ΔV_OUT/ΔI_OUT	Load regulation	V_IN = 13 V, V_OUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, I_OUT = 0 A to 7 A, referenced to V_OUT at I_OUT = I_{OUT_MAX}	0%		1%
V_{TH_PG}	Power Good deassertion threshold in percentage of target V_OUT	V_OUT rising	105.5%	108%	110.5%
V_{TH_PG}		V_OUT falling	89.5%	92%	94.5%
R_{DSON_DRVH}	Driver DRVH resistance	Source, IDRVH = –50 mA		3		Ω
R_{DSON_DRVH}	Driver DRVH resistance	Sink, IDRVH = 50 mA		2		Ω
R_{DSON_DRVL}	Driver DRVL resistance	Source, IDRVL = –50 mA		3		Ω
R_{DSON_DRVL}	Driver DRVL resistance	Sink, IDRVL = 50 mA		0.4		Ω
R_DIS	Output auto-discharge resistance	BUCK1_DIS[1:0] = 01		100		Ω
		BUCK1_DIS[1:0] = 10		200		Ω
		BUCK1_DIS[1:0] = 11		500		Ω
C_BOOT	Bootstrap capacitance			100		nF
R_{ON_BOOT}	Bootstrap switch ON resistance				20	Ω

(1) BUCKx_VID[6:0] = 0000001 – 0011000

4.8 Electrical Characteristics: Synchronous Buck Converters

over recommended input voltage range, T_A = –40°C to 85°C and T_A = 25°C for typical values (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
BUCK3, BUCK4, BUCK5
V_IN	Power input voltage		4.5	5	5.5	V
V_OUT	DC output voltage VID range and options	VID step size = 10 mV, BUCKx_VID[6:0] progresses from 0000001 to 1111111	0.41		1.67	V
		VID step size = 12.5 mV, BUCKx_VID[6:0] progresses from 0000001 to 1111111	0.4125		1.9875
		VID step size = 25 mV, BUCKx_VID[6:0] progresses from 0000001 to 1111111	0.425		3.575
	BUCK3 output voltage	Set by BUCK3_VID[6:0], 25-mV step size selected		1.05		V
	BUCK4 output voltage	Set by BUCK4_VID[6:0], 25-mV step size selected		3.3
	BUCK5 output voltage	Set by BUCK5_VID[6:0], 25-mV step size selected		1.5
	DC output voltage accuracy	V_OUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, I_OUT = 1.5 A	–2%		2%
	DC output voltage accuracy	V_OUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, I_OUT = 100 mA	–2.5%		2.5%
	Total output voltage accuracy (DC + ripple) in DCM	I_OUT = 10 mA, V_OUT ≤ 1 V	–30		40	mV
SR(V_OUT)	Output DVS slew rate		2.5	3.125		mV/µs
I_OUT	Continuous DC output current				3	A
I_{IND_LIM}	HSD FET current limit		4.3		7	A
I_Q	Quiescent current	V_IN = 5 V, V_OUT = 1 V		35		µA
ΔV_OUT/ΔV_IN	Line regulation	V_OUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, I_OUT = 1.5 A	–0.5%		0.5%
ΔV_OUT/ΔI_OUT	Load regulation	V_IN = 5 V, V_OUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, I_OUT = 0 A to 3 A, referenced to V_OUT at I_OUT = 1.5 A	–0.2%		2%
V_{TH_PG}	Power Good deassertion threshold in percentage of target V_OUT	V_OUT rising		108%
V_{TH_PG}		V_OUT falling		92%
V_{TH_HYS_PG}	Power Good reassertion hysteresis entering back into V_{TH_PG}	V_OUT rising or falling		3%
R_DIS	Output auto-discharge resistance	BUCK3_DIS[1:0] = 01		100		Ω
		BUCK3_DIS[1:0] = 10		200
		BUCK3_DIS[1:0] = 11		500

4.9 Electrical Characteristics: LDOs

over recommended input voltage range, T_A = –40°C to 85°C and T_A = 25°C for typical values (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
LDOA1
V_IN	Input voltage		4.5	5	5.5	V
V_OUT	DC output voltage	Set by LDOAx_VID[3:0]		3.3
V_OUT	Accuracy	I_OUT = 0 to 200 mA	–2%		2%	V
I_OUT	DC output current				200	mA
ΔV_OUT/ΔV_IN	Line regulation	I_OUT = 40 mA	–0.5%		0.5%
ΔV_OUT/ΔI_OUT	Load regulation	I_OUT = 10 mA to 200 mA	–2%		2%
I_OCP	Overcurrent protection	V_IN = 5 V, Measured with output shorted to ground	500			mA
V_{TH_PG}	Power Good deassertion threshold in percentage of target V_OUT	V_OUT rising		108%
V_{TH_PG}		V_OUT falling		92%
t_STARTUP	Start-up time	Measured from EN = H to reach 95% of final value, C_OUT = 4.7 µF			500	µs
I_Q	Quiescent current	I_OUT = 0 A		23		µA
C_OUT	External output capacitance		2.7	4.7	10	µF
C_OUT	ESR				100	mΩ
R_DIS	Output auto-discharge resistance	LDOA1_DIS[1:0] = 01		100		Ω
		LDOA1_DIS[1:0] = 10		190		Ω
		LDOA1_DIS[1:0] = 11		450		Ω
LDOA2 and LDOA3
V_IN	Power input voltage		V_OUT + V_DROP ⁽¹⁾	1.8	1.98	V
V_OUT	LDOA2 DC output voltage	Set by LDOAx_VID[3:0]		0.7		V
	LDOA3 DC output voltage	Set by LDOAx_VID[3:0]		1.2		V
	DC output voltage accuracy	I_OUT = 0 to 600 mA	–2%		3%
I_OUT	DC output current				600	mA
V_DROP	Dropout voltage	V_OUT = 0.99 × V_{OUT_NOM}, I_OUT = 600 mA			350	mV
ΔV_OUT/ΔV_IN	Line regulation	I_OUT = 300 mA	–0.5%		0.5%
ΔV_OUT/ΔI_OUT	Load regulation	I_OUT = 10 mA to 600 mA	–2%		2%
I_OCP	Overcurrent protection	Measured with output shorted to ground	0.65	1.25		A
V_{TH_PG}	Power Good assertion threshold in percentage of target V_OUT	V_OUT rising		108%
V_{TH_PG}		V_OUT falling		92%
t_STARTUP	Start-up time	Measured from EN = H to reach 95% of final value, C_OUT = 4.7 µF			500	µs
I_Q	Quiescent current	I_OUT = 0 A		20		µA
LDOA2 and LDOA3 (continued)
PSRR	Power supply rejection ratio	f = 1 kHz, V_IN = 1.8 V, V_OUT = 1.2 V, I_OUT = 300 mA, C_OUT = 2.2 µF – 4.7 µF		48		dB
PSRR	Power supply rejection ratio	f = 10 kHz, V_IN = 1.8 V, V_OUT = 1.2 V, I_OUT = 300 mA, C_OUT = 2.2 µF – 4.7 µF		30		dB
C_OUT	External output capacitance		2.2	4.7	10	µF
C_OUT	ESR				100	mΩ
R_DIS	Output auto-discharge resistance	LDOA2_DIS[1:0] = 01		80		Ω
		LDOA2_DIS[1:0] = 10		180
		LDOA2_DIS[1:0] = 11		475
VTT LDO
V_IN	Power input voltage			1.2	3.3	V
V_OUT	DC output voltage	V_IN = 1.2 V, Measured at VTTFB pin		V_IN / 2		V
	DC output voltage accuracy	Relative to V_IN / 2, I_OUT ≤ 10 mA, 1.1 V ≤ V_IN ≤ 1.35 V	–10		10	mV
	DC output voltage accuracy	Relative to V_IN/ 2, I_OUT ≤ 500 mA, 1.1 V ≤ V_IN ≤ 1.35 V	–25		25	mV
I_OUT	DC output current	sink(–) and source(+)	–500		500	mA
ΔV_OUT/ΔI_OUT	Load regulation	1.1 V ≤ V_IN ≤ 1.35 V, I_OUT = –500 mA to 500 mA	–4%		4%
I_OCP	Overcurrent protection	Measured with output shorted to ground	0.95			A
V_{TH_PG}	Power Good deassertion threshold in percentage of target V_OUT	V_OUT rising		110%
V_{TH_PG}		V_OUT falling		95%
V_{TH_HYS_PG}	Power Good reassertion hysteresis entering back into V_{TH_PG}			5%
I_Q	Total ground current	V_IN = 1.2 V, I_OUT = 0 A			240	µA
I_LKG	OFF leakage current	V_IN = 1.2 V, disabled			1	µA
C_IN	External input capacitance		10			µF
C_OUT	External output capacitance		35			µF
R_DIS	Output auto-discharge resistance	VTT_DIS = 0	1000			kΩ
R_DIS	Output auto-discharge resistance	VTT_DIS = 1	60	80	100	Ω

(1) It must be equal to or greater than 1.62 V.

4.10 Electrical Characteristics: Load Switches

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SWA1
V_IN	Input voltage range		0.5	1.8	3.3	V
I_OUT	DC output current				300	mA
R_DSON	ON resistance	V_IN = 1.8 V, measured from PVINSWA1 pin to SWA1 pin at I_OUT = I_OUT,MAX		60	93	mΩ
R_DSON	ON resistance	V_IN = 3.3 V, measured from PVINSWA1 pin to SWA1 pin at I_OUT = I_OUT,MAX		100	165	mΩ
V_{TH_PG}	Power Good deassertion threshold in percentage of target V_OUT	V_OUT rising		108%
V_{TH_PG}		V_OUT falling		92%
V_{TH_HYS_PG}	Power Good reassertion hysteresis entering back into V_{TH_PG}	V_OUT rising or falling		2%
I_INRUSH	Inrush current upon turnon	V_IN = 3.3 V, C_OUT = 0.1 µF			10	mA
I_Q	Quiescent current	V_IN = 3.3 V, I_OUT = 0 A		10.5		µA
I_Q	Quiescent current	V_IN = 1.8 V, I_OUT = 0 A		9		µA
I_LKG	Leakage current	Switch disabled, V_IN = 1.8 V		7	370	nA
I_LKG	Leakage current	Switch disabled, V_IN = 3.3 V		10	900	nA
C_OUT	External output capacitance			0.1		µF
R_DIS	Output auto-discharge resistance	SWA1_DIS[1:0] = 01		100		Ω
		SWA1_DIS[1:0] = 10		200
		SWA1_DIS[1:0] = 11		500
SWB1_2
V_IN	Input voltage range		0.5	1.8	3.3	V
I_OUT	DC current per output				400	mA
R_DSON	ON resistance	V_IN = 1.8 V, measured from PVINSWB1_B2 pin to SWB1/SWB2 pin at I_OUT = I_OUT,MAX		68	92	mΩ
R_DSON	ON resistance	V_IN = 3.3 V, measured from PVINSWB1_B2 pin to SWB1/SWB2 pin at I_OUT = I_OUT,MAX		75	125	mΩ
V_{TH_PG}	Power Good deassertion threshold in percentage of target V_OUT	V_OUT rising		108%
V_{TH_PG}		V_OUT falling		92%
V_{TH_HYS_PG}	Power Good reassertion hysteresis entering back into V_{TH_PG}	V_OUT rising or falling		2%
I_INRUSH	Inrush current upon turning on	V_IN = 3.3 V, C_OUT = 0.1 µF			10	mA
I_Q	Quiescent current	V_IN = 3.3 V, I_OUT = 0 A		10.5		µA
I_Q	Quiescent current	V_IN = 1.8 V, I_OUT = 0 A		9		µA
I_LKG	Leakage current	Switch disabled, V_IN = 1.8 V		7	460	nA
I_LKG	Leakage current	Switch disabled, V_IN = 3.3 V		10	1150	nA
C_OUT	External output capacitance			0.1		µF
R_DIS	Output auto-discharge resistance	SWBx_DIS[1:0] = 01		100		Ω
		SWBx_DIS[1:0] = 10		200
		SWBx_DIS[1:0] = 11		500

4.11 Digital Signals: I²C Interface

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A = 25°C) (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OL	Low-level output voltage	V_{PULL_UP} = 1.8 V			0.4	V
V_IH	High-level input voltage		1.2			V
V_IL	Low-level input voltage				0.4	V
I_LKG	Leakage current	V_{PULL_UP} = 1.8 V		0.01	0.3	µA
R_PULL-UP	Pullup resistance	Standard mode			8.5	kΩ
		Fast mode			2.5
		Fast mode plus			1
C_OUT	Total load capacitance per pin				50	pF

4.12 Digital Input Signals (CTLx)

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A = 25°C) (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	High-level input voltage		0.85			V
V_IL	Low-level input voltage				0.4	V

4.13 Digital Output Signals (IRQB, GPOx)

Over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A = 25°C) (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OL	Low-level output voltage	I_OL< 2 mA			0.4	V
I_LKG	Leakage current	V_{PULL_UP} = 1.8 V			0.35	µA

4.14 Timing Requirements

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A = 25°C) (unless otherwise noted)

		MAX	UNIT
I²C INTERFACE
f_CLK	Clock frequency (standard mode)	100	kHz
	Clock frequency (fast mode)	400	kHz
	Clock frequency (fast mode plus)	1000	kHz
t_r	Rise time (standard mode)	1000	ns
	Rise time (fast mode)	300	ns
	Rise time (fast mode plus)	120	ns
t_f	Rise time (standard mode)	300	ns
	Rise time (fast mode)	300	ns
	Rise time (fast mode plus)	120	ns

4.15 Switching Characteristics

over operating free-air temperature range and over recommended input voltage range (typical values are at T_A = 25°C) (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
BUCK CONTROLLERS
t_PG	Total turnon time	Measured from enable going high to when output reaches 90% of target value.	550	850	µs
T_ON,MIN	Minimum on-time of DRVH		50		ns
T_DEAD	Driver dead-time	DRVH off to DRVL on	15		ns
T_DEAD	Driver dead-time	DRVL off to DRVH on	30		ns
f_SW	Switching frequency	Continuous-conduction mode, V_IN = 13 V, V_OUT ≥ 1 V	1000		kHz
BUCK CONVERTERS
t_PG	Total turnon time	Measured from enable going high to when output reaches 90% of target value.	250	1000	µs
f_SW	Switching frequency	Continuous-conduction mode, V_OUT = 1 V, I_OUT = 1 A	1.7		MHz
		Continuous-conduction mode, V_OUT = 1.05 V, I_OUT = 1 A	1.9		MHz
		Continuous-conduction mode, V_OUT = 1.8 V, I_OUT = 1 A	2.5		MHz
LDOAx
t_STARTUP	Start-up time	Measured from enable going high to when output reaches 95% of final value, V_OUT = 1.2 V, C_OUT = 4.7 µF	180		µs
VTT LDO
t_STARTUP	Start-up time	Measured from enable going high to PG assertion, V_OUT = 0.675 V, C_OUT = 40 µF	22		µs
SWA1
t_TURN-ON	Turnon time	Measured from enable going high to reach 95% of final value, V_IN = 3.3 V, C_OUT = 0.1 µF	0.85		ms
t_TURN-ON	Turnon time	Measured from enable going high to reach 95% of final value, V_IN = 1.8 V, C_OUT = 0.1 µF	0.63		ms
SWB1_2
t_TURN-ON	Turnon time	Measured from enable going high to reach 95% of final value, V_IN = 3.3 V, C_OUT = 0.1 µF	1.1		ms
t_TURN-ON	Turnon time	Measured from enable going high to reach 95% of final value, V_IN = 1.8 V, C_OUT = 0.1 µF	0.82		ms

4.16 Typical Characteristics

Measurements done at 25°C.

Figure 4-1 BUCK2 Controller Start Up

Figure 4-3 BUCK1 Efficiency at V_IN = 13 V

Figure 4-5 BUCK3 Efficiency at V_IN = 5 V

Figure 4-2 BUCK3 Converter Start Up

Figure 4-4 BUCK1 Efficiency at V_IN = 18 V