ZHCSKD3A November   2019  – February 2021 TPS6521815

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1. 3.1 Simplified Schematic
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Wake-Up and Power-Up and Power-Down Sequencing
        1. 8.3.1.1  Power-Up Sequencing
        2. 8.3.1.2  Power-Down Sequencing
        3. 8.3.1.3  Strobe 1 and Strobe 2
        4. 8.3.1.4  Supply Voltage Supervisor and Power-Good (PGOOD)
        5. 8.3.1.5  Backup Supply Power-Good (PGOOD_BU)
        6. 8.3.1.6  Internal LDO (INT_LDO)
        7. 8.3.1.7  Current Limited Load Switches
          1. 8.3.1.7.1 Load Switch 1 (LS1)
          2. 8.3.1.7.2 Load Switch 2 (LS2)
          3. 8.3.1.7.3 Load Switch 3 (LS3)
        8. 8.3.1.8  LDO1
        9. 8.3.1.9  Coin Cell Battery Voltage Acquisition
        10. 8.3.1.10 UVLO
        11. 8.3.1.11 Power-Fail Comparator
        12. 8.3.1.12 Battery-Backup Supply Power-Path
        13. 8.3.1.13 DCDC3 and DCDC4 Power-Up Default Selection
        14. 8.3.1.14 I/O Configuration
          1. 8.3.1.14.1 Configuring GPO2 as Open-Drain Output
          2. 8.3.1.14.2 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
        15. 8.3.1.15 Push Button Input (PB)
          1. 8.3.1.15.1 Signaling PB-Low Event on the nWAKEUP Pin
          2. 8.3.1.15.2 Push Button Reset
        16. 8.3.1.16 AC_DET Input (AC_DET)
        17. 8.3.1.17 Interrupt Pin (INT)
        18. 8.3.1.18 I2C Bus Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
      2. 8.4.2 OFF
      3. 8.4.3 ACTIVE
      4. 8.4.4 SUSPEND
      5. 8.4.5 RESET
    5. 8.5 Programming
      1. 8.5.1 Programming Power-Up Default Values
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Applications Without Backup Battery
      2. 9.1.2 Applications Without Battery Backup Supplies
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Filter Design
        2. 9.2.2.2 Inductor Selection for Buck Converters
        3. 9.2.2.3 Output Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

8.3.1.5 Backup Supply Power-Good (PGOOD_BU)

PGOOD_BU is a push-pull output indicating if DCDC5 and DCDC6 are in regulation. The output is driven to high when both rails are in regulation, and driven low if at least one of the rails is below the power-good threshold. The output-high level is equal to the output voltage of DCDC6.

PGOOD_BU is the logical and between PGOOD (DCDC5) and PGOOD (DCDC6), and has no delay time built-in. Unlike the main power-good, a fault on DCDC5 or DCDC6 does not trigger the power-down sequencer, does not disable any of the rails in the system, and has no effect on the PGOOD pin. DCDC5 and DCDC6 recover automatically once the fault is removed.

Note:

In this example, the power-down is triggered by a fault on DCDC3.

This timing diagram assumes each rail powers up within the strobe delay time. If a rail takes longer than the strobe delay time to power up, the next rail will wait for the previous rail to reach its PGOOD voltage, and then may wait an additional 1 ms until it is enabled.

GUID-501CF4EE-F7E5-4742-930C-94350E6B0286-low.gif
Sequence shown for TPS65218D0 and TPS6521825 variants. For TPS6521815 variant, order and timing of DCDC5 and DCDC6 can be modified using registers SEQ1-2 and SEQ5 in GUID-6BC168C1-81BD-4A6E-8C99-0931B4B82DD6.html#TPS65218.
Figure 8-9 Typical Power-Up Sequence of DCDC5 and DCDC6
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