The TPS65263-Q1 requires a start condition, a valid I²C address, a register address byte, and a data byte for a single update. After the receipt of each byte, TPS65263-Q1 device acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I²C address selects the TPS65263-Q1. TPS65263-Q1 performs an update on the falling edge of the LSB byte.

When the TPS65263-Q1 is in hardware shutdown (EN1, EN2, and EN3 pin tied to ground) the device cannot be updated through the I²C interface. Conversely, the I²C interface is fully functional during software shutdown (EN1, EN2, and EN3 bit = 0).

Figure 7-15 I²C Write Data Format

Figure 7-16 I²C Read Data Format