8.1.1 Transient Response

As with any regulator, increasing the size of the output capacitor reduces overshoot or undershoot magnitude but increases duration of the transient. The TPS717xx has an ultra-wide loop bandwidth that allows it to respond quickly to load transient events. As with any regulator, the loop bandwidth is finite and the initial transient voltage peak is controlled by the sizing of the output capacitor. Typically, larger output capacitors reduce the peak while also reducing the bandwidth of the LDO, slowing the response time.

8.1.2 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF or larger low equivalent series resistance (ESR) capacitor from IN to GND near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability.

The TPS717xx is designed to be stable with ceramic output capacitors of values 1 μF or larger. The X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. The maximum ESR of the output capacitor must be less than 1 Ω.

8.1.3 Dropout Voltage

The TPS717xx uses a PMOS pass transistor to achieve low dropout. When (V_IN – V_OUT) is less than the dropout voltage (V_DO), the PMOS pass device is in its linear region of operation and the input-to-output resistance is the R_DSon of the PMOS pass element. V_DO scales approximately with output current because the PMOS device functions as a resistor in dropout.

As with any linear regulator, PSRR and transient response are degraded when (V_IN – V_OUT) approaches dropout. This effect is illustrated in Figure 15 through Figure 17 in Typical Characteristics.

8.1.4 Output Noise

In most LDOs, the band gap is the dominant noise source. If a noise reduction capacitor (C_NR) is used with the TPS717xx, the band gap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01-μF (minimum) noise reduction capacitor; for the adjustable version, smaller value resistors in the output resistor divider reduce noise. A parallel combination that gives 2.5 μA of divider current has the same noise performance as a fixed voltage version.

Equation 2 approximates the total noise referred to the feedback point (FB pin) when C_NR = 0.01 μF:

Equation 2.

8.2.1 Application for Fixed Voltage Versions and Adjustable Voltage Version

Figure 33 shows the basic circuit connections for the fixed voltage options. Figure 34 gives the connections for the adjustable output version (TPS71701). Note that the NR pin is not available on the adjustable version.

Figure 33. Typical Application Circuit
(Fixed Voltage Versions)

Figure 34. Typical Application Circuit
(Adjustable Voltage Version)

8.2.1.2 Detailed Design Procedure

For the adjustable version (TPS71701), the NR pin is replaced with a feedback (FB) pin. The voltage on this pin sets the output voltage and is determined by the values of R₁ and R₂. The values of R₁ and R₂ can be calculated for any voltage using the formula given in Equation 3:

Equation 3.  

The value of R₂ directly impacts the operation of the device and must be chosen in the range of approximately
160 kΩ to 320 kΩ. Sample resistor values for common output voltages are shown in Table 3.

Table 3. Sample 1% Resistor Values for Common Output Voltages

VOUT	R1	R2
1	80.6 kΩ	324 kΩ
1.2	162 kΩ	324 kΩ
1.5	294 kΩ	332 kΩ
1.8	402 kΩ	324 kΩ
2.5	665 kΩ	316 kΩ
3.3	1.02 MΩ	324 kΩ
5	1.74 MΩ	332 kΩ

8.2.1.3 Application Curve

Figure 35. Load Transient Response

8.2.2 Powering a PLL Integrated on an SOC

Figure 36 shows the TPS71701 powering a phase-locked loop (PLL) that is integrated into a system-on-a-chip (SOC).

Figure 36. Typical Application Circuit: PLL on an SOC

Use the input and output capacitors to ensure the voltage transient requirements. A 1-µF input and 1-µF output capacitor are selected to maximize the capacitance and minimize capacitor size.

R₂ is chosen to be 158 kΩ for optimal noise and PSRR, and by Equation 4, R₁ is selected to be 402 kΩ. Both R₁ and R₂ must be 1% tolerance resistors to meet the dc accuracy specification over line, load, and temperature.