10.1 Layout Guidelines

An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage droop on the input of the device during load transients, connect the capacitance on IN and BIAS as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can therefore improve stability. To achieve optimal transient performance and accuracy, connect the top side of R₁ in Figure 27 as close as possible to the load. This connection minimizes the voltage droop on BIAS during transient conditions and can improve the turn-on response.

10.2 Layout Example

Figure 40. Layout Schematic (VQFN Packages)

10.3 Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation.

Power dissipation of the device depends on input voltage and load conditions, and can be calculated using Equation 5:

Equation 5.

Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation.

On the VQFN (RGW, RGR) packages, the primary conduction path for heat is through the exposed pad to the PCB. The pad can be connected to ground or left floating; however, the pad must be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. On the DDPAK (KTW) package, the primary conduction path for heat is through the tab to the PCB. Connect that tab to ground. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be estimated using Equation 6:

Equation 6.

Knowing the maximum R_θJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 41.

NOTE:

θ_JA value at board size of 9 in² (that is, 3 in × 3 in) is a JEDEC standard.

Figure 41. θ_JA versus Board Size

Figure 41 shows the variation of θ_JA as a function of ground plane copper area in the board. Figure 41 is intended only as a guideline to demonstrate the affects of heat spreading in the ground plane; do not use Figure 41 to estimate actual thermal performance in real application environments.

10.4 Thermal Considerations

A better method of estimating the thermal measure comes from using the thermal metrics Ψ_JT and Ψ_JB, as shown in Thermal Information . These metrics are a more accurate representation of the heat transfer characteristics of the die and the package than R_θJA. The junction temperature can be estimated with the corresponding formulas given in Equation 7.

Equation 7.

where

• P_D is the power dissipation shown by Equation 5,
• T_T is the temperature at the center-top of the IC package, and
• T_B is the PCB temperature measured 1 mm away from the IC package on the PCB surface (see Figure 42).

For more information about measuring T_T and T_B, see the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com.

1. T_T is measured at the center of both the X- and Y-dimensional axes.

2. T_B is measured below the package lead on the PCB surface.

Figure 42. Measuring Points for T_T and T_B

Compared with θ_JA, the thermal metrics Ψ_JT and Ψ_JB are less independent of board size, but do have a small dependency on board size and layout. Figure 43 shows characteristic performance of Ψ_JT and Ψ_JB versus board size.

Referring to Figure 43, the RGW package thermal performance has negligible dependency on board size. The KTW package, however, does have a measurable dependency on board size. This dependency exists because the package shape is not point symmetric to an IC center. In the KTW package, for example (see Figure 42), silicon is not beneath the measuring point of T_T which is the center of the X and Y dimension, so that Ψ_JT has a dependency. Also, because of that non-point symmetry, device heat distribution on the PCB is not point symmetric either, so that Ψ_JB has a greater dependency on board size and layout.

Figure 43. Ψ_JT and Ψ_JB versus Board Size

For a more detailed discussion of why TI does not recommend using θ_JC(top) to determine thermal characteristics, refer to the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com. Also, refer to the application note IC Package Thermal Metrics (SPRA953) (also available on the TI website) for further information.