10.1 Layout Guidelines

10.2 Layout Examples

Figure 28. TPS79601 (Adjustable Voltage Version)—DRB Layout Example

Figure 29. TPS796xx (Fixed Voltage Versions)—DRB Layout Example

10.3 Thermal Considerations

Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation.

Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 4:

Equation 4.

Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation.

On the VSON (DRB) package, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. On both SOT-223 (DCQ) and TO-263 (KTT) packages, the primary conduction path for heat is through the tab to the PCB. That tab should be connected to ground. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 5:

Equation 5. '

Knowing the maximum R_θJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 30.

θJA value at board size of 9in2 (that is, 3in × 3in) is a JEDEC standard.

Figure 30. Θ_JA vs Board Size

Figure 30 shows the variation of θ_JA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments.

10.4 Estimating Junction Temperature

Using the thermal metrics Ψ_JT and Ψ_JB, as shown in Thermal Information, the junction temperature can be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older θ_JC,Top parameter is listed as well.

Equation 6.

where

• P_D is the power dissipation shown by Equation 5
• T_T is the temperature at the center-top of the IC package
• T_B is the PCB temperature measured 1mm away from the IC package on the PCB surface (as Figure 32 shows).

For more information about measuring T_T and T_B, see the application note SBVA025, Using New Thermal Metrics, available at www.ti.com.

By looking at Figure 31, the new thermal metrics (Ψ_JT and Ψ_JB) have very little dependency on board size. That is, using Ψ_JT or Ψ_JB with Equation 6 is a good way to estimate T_J by simply measuring T_T or T_B, regardless of the application board size.

Figure 31. Ψ_JT And Ψ_JB vs Board Size

For a more detailed discussion of why TI does not recommend using θ_JC(top) to determine thermal characteristics, refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further information, refer to application report SPRA953, IC Package Thermal Metrics, also available on the TI website.

1. T_T is measured at the center of both the X- and Y-dimensional axes.

2. T_B is measured below the package lead on the PCB surface.

Figure 32. Measuring Points For T_T and T_B