ZHCSOO0C september 2021 – june 2023 TPS7A94
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Output Voltage Setting and Regulation
- 7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)
- 7.3.3 Programmable Current Limit and Power-Good Threshold
- 7.3.4 Programmable Soft Start (NR/SS Pin)
- 7.3.5 Precision Enable and UVLO
- 7.3.6 Active Discharge
- 7.3.7 Thermal Shutdown Protection (TSD)
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1
Application Information
- 8.1.1 Output Voltage Restart (Overshoot Prevention Circuit)
- 8.1.2 Precision Enable (External UVLO)
- 8.1.3 Undervoltage Lockout (UVLO) Operation
- 8.1.4 Dropout Voltage (VDO)
- 8.1.5 Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)
- 8.1.6 Adjusting the Factory-Programmed Current Limit
- 8.1.7 Programmable Soft-Start and Noise-Reduction (NR/SS Pin)
- 8.1.8 Inrush Current
- 8.1.9 Optimizing Noise and PSRR
- 8.1.10 Adjustable Operation
- 8.1.11 Paralleling for Higher Output Current and Lower Noise
- 8.1.12 Recommended Capacitor Types
- 8.1.13 Load Transient Response
- 8.1.14 Power Dissipation (PD)
- 8.1.15 Estimating Junction Temperature
- 8.1.16 TPS7A94EVM-046 Thermal Analysis
- 8.2 Typical Application
- 8.3 Power Supply Recommendations
- 8.4 Layout
- 8.1
Application Information
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
5 Pin Configuration and Functions
Figure 5-1 DSC
Package,10-Pin WSON(Top View)Pin Functions
| PIN | I/O(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | WSON | ||
| EN_UV | 3 | I | Precision enable and undervoltage lockout pin; see the Precision Enable (External UVLO) section for details. |
| FB_PG | 5 | I | Power-good feedback pin. This pin has a dual function: this pin programs the PG pin output threshold and scales the factory-programmed current limit value specified in the Electrical Characteristics table to either 100%, 80%, or 60%. See the Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin) section for details. |
| GND | 6 | G | Ground pin; see the Board Layout section for details. |
| IN | 1, 2 | P | Input voltage supply pin; see the Recommended Capacitor Types section and the Recommended Operating Conditions table for additional information. |
| NR/SS | 7 | I | Output voltage set and noise-reduction pin; see the Programmable Soft-Start and Noise-Reduction (NR/SS Pin) section for details. |
| OUT | 9, 10 | O | Regulated output pin; see the Load Transient Response section for additional information. |
| PG | 4 | O | Open-drain, power-good indicator pin for the LDO output voltage. See the Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin) section for additional information. |
| SNS | 8 | I | Output sense pin. This pin is the input to the noninverting terminal of the error amplifier; see the Board Layout section for details. |
| Thermal pad | G | The thermal pad is electrically connected to the GND pin; see the Board Layout section for details. | |
(1) I = input, O = output, I/O =
input or output, G = ground, P = power.