8.2.1.1 Adjustable Output Voltage (Feedback Circuit)

The output voltage of the TPS7H1101A-SP can be set to a user-programmable level between 0.8 V and 6.65 V. Achieve this by using a resistor divider connected between V_OUT, FB, and GND terminals. R_TOP connected between V_OUT and V_FB, and R_BOTTOM connected between V_FB and GND.

Use Equation 3 to determine V_OUT.

Equation 3.

where

• V_FB = 0.605 V

8.2.1.2 PCL

PCL resistor, R_PCL, sets the overcurrent limit activation point and can be calculated per Equation 4.

Figure 11 shows the output load current (I_OUT) versus PCL terminal current (I_CL).

A suitable resistor R_PCL must be chosen to ensure the CS terminal is within its operating range of 0.3 V to V_IN.

The maximum PCL is 3.5 A. The range of resistor that can be used on the PCL terminal to GND is 8.2 kΩ to 160 kΩ.

	VIN = 2.3 V	VOUT = 1.8 V	y = 47394x + 0.0403

Figure 11. I_OUT (A) vs I_PCL (µA)

8.2.1.3 High-Side Current Sense

Figure 12 shows the cascode NMOS current mirror. V_cs must be in the range as specified in the Electrical Characteristics table. The following example shows the typical calculation of R_cs.

Equation 5.

Equation 6.

where

• I_LOAD is the output load current.
• CSR is the current sense ratio.

When V_IN = 2.3 V, select V_CS = 2.05 V, I_LOAD = 3 A, CSR = 47394, and I_offset = 0.1899 A, then I_CS = 67.306 µA and R_CS = 3.714 kΩ.

Figure 12. Cascode NMOS Current Mirror

For TPS7H1101A-SP, Figure 13 shows the typical curve V_CS vs I_OUT for V_IN = 2.28 V and R_CS = 3.65 kΩ. A resistor connected from the CS terminal to V_IN indicates voltage proportional to the output current.

Monitoring current in the CS terminal (I_CS vs I_OUT) indicates the current sense ratio between the main PMOSFET and the current sense MOSFET as shown in Figure 14.

Figure 15 shows I_OUT vs I_CS when the voltage on CS terminal is varied from 0.3 V to 7 V.

VIN = 2.3 V

VOUT = 1.8 V

y = –0.078x + 2.2853

Figure 13. V_CS (V) vs I_OUT (A)

y = 49917x – 0.2466

Figure 15. I_OUT (A) vs I_CS (A)

VIN = 2.3 V

VOUT = 1.8 V

Figure 14. I_OUT (A) vs I_CS (A)

8.2.1.4 Current Foldback

1. The TPS7H1101A-SP has a current foldback feature which can be enabled when the CS terminal is held high. Shorting CS low disables the foldback current limit. If the foldback current limit is disabled, then the LDO will begin regulating again as soon as the current falls below the clamp threshold.
2. With foldback current limit enabled, when current limit trip point is activated,
   1. Output voltage drops low, and
   2. Output current folds back to approximately 50% of the current limit trip point.
   This results in minimizing the power loss under fault conditions. Monitoring the voltage at the CS terminal indicates voltage proportional to the output current.

8.2.1.5 Transient Response

Figure 16, Figure 17, and Figure 18 indicate the transient response behavior of the LDO for 50% step load change.

Channel 1: Input voltage

Channel 2: Output voltage overshoot/undershoot

Channel 3: Step load in current

Figure 16. Load Transient Response: Step Load 0.1 to 1.6 A, V_IN = 2.3 V, V_OUT = 1.8 V

Figure 18. Expanded View Undershoot

Figure 17. Expanded View Overshoot

8.2.1.6 Current Sharing

For demanding load requirements, multiple LDOs can be paralleled as indicated in Figure 20. In parallel mode, the CS terminal of LDO1 must be connected to the PCL terminal of LDO2 via a series resistor, R_CL, and CS terminal of LDO2 must be connected to PCL terminal of LDO1 via series resistor, R_CL. The typical value of R_CL in parallel operation is 3.75 kΩ for current limit > 6 A. In parallel configuration, R_CL (resistor from PCL to GND) and R_CS (resistor from CS terminal to V_IN) must be left open (unpopulated). The R_CL value must be selected so that the operating condition of the CS terminal is maintained, as specified in the Electrical Characteristics table. The current from PCL through RCL of LDO1 is determined by the output load current of LDO2 divided by the CSR. Hence, the voltage at CS terminal of the LDO1 is 0.605 V – ((output load current of LDO2 + 0.2458) / CSR × R_CL).

Alternately, it can also provide twice the output current to meet system needs. When using two LDOs in parallel operation for higher output load current, use POL TPS50601-SP as an input source.

Figure 19. LDO Current Share

Figure 20. Block Diagram (Parallel Operation)

8.2.1.7 Compensation

Figure 21 shows a generic block diagram for TPS7H1101A-SP LDO with external compensation components. LDO incorporates nested loops, thus providing the high gain necessary to meet design performance.

Figure 21. TPS7H1101A-SP Compensation

Resistor divider composed of R_top and R_bottom determine the output voltage set points as indicated by Equation 3.

Output capacitor C_OUT introduces a pole and a zero as shown in the following.

Equation 7.

Equation 8.

The TPS7H1101A-SP was designed so that the ESR of the output capacitor will not have a strong influence on the response of the LDO. However, an optional capacitor, C_x, can be added in parallel with the bottom feedback resistor to introduce a pole to cancel F_{z_co}. Equation 9 shows how to calculate the location of the pole introduced by C_x. To cancel the zero directly, F_p should be equal to F_{z_co}.

Equation 9.

C_x is calculated to be 1000 pF for C_o = 220 µF, C_esr = 45 mΩ, and R_bottom = 10 kΩ.

Internal compensation in the LDO cancels the output capacitor pole introduced by C_OUT and R_L.

C_comp introduces a dominant pole at low frequency. TI recommends that a C_comp value of 10 nF.

8.2.1.8 Output Noise

Output noise is measured using an HP3495A. Figure 22 and Figure 23 show noise of the TPS7H1101A-SP in µV/√Hz vs frequency.

VIN = 2 V	VOUT = 1.8 V at 3 A
CIN = 220 µF	CLOAD = 220 µF

Figure 22. RMS Noise (10 Hz to 100 kHz) = 20.33 µVrms

VIN = 7 V	VOUT = 6.7 V at ILOAD = 3 A
CIN = 220 µF	CLOAD = 220 µF

Figure 23. RMS Noise (10 Hz to 100 kHz)
= 31.68 µVrms

8.2.1.9 Capacitors

TPS7H1101A-SP requires the use of a combination of tantalum and ceramic capacitors to achieve good volume to capacitance ratio. Table 2 highlights some of the capacitors used in the device. TI recommends to follow proper derating guidelines as recommended by the capacitor manufacturer based upon output voltage and operating temperature.

Note that polymer-based tantalum capacitors must be derated to at least 60% of rated voltage, whereas manganese oxide (MnO₂) based tantalum capacitors should be derated to 33% of rated voltage depending upon the operating temperature.

TI recommends to use a tantalum capacitor along with a 0.1-µF ceramic capacitor. The device is stable for input and output tantalum capacitor values of 10 µF to 220 µF with the ESR range of 10 mΩ to 2 Ω. However, the dynamic performance of the device varies based on load conditions and the capacitor values used.

TI recommends a minimum output capacitor of 22 µF with ESR of 1 Ω or less to prevent oscillations. X7R dielectrics are preferred. See Table 2 for various capacitor recommendations.