SLVSFZ4A December 2020 – February 2021 TPS929121-Q1
PRODUCTION DATA
Each FlexWire bus supports maximum 16 slave devices. The TPS929121-Q1 has 3 pinouts including ADDR2, ADDR1, and ADDR0 for slave address configuration. There are additional 4-bit EEPROM register to program the slave address of the TPS929121-Q1. The EEPROM register EEP_INTADDR sets the device slave address by either address pins setup or internal EEPROM register code.
If EEP_INTADDR is 1, the device uses the binary code burnt in EEPROM register EEP_DEVADDR as slave address as shown in Table 8-7 . In this conditions, the ADDR2 pin is used for external clock input for internal PWM generator as described in External Clock Input for PWM Generator (CLK), however ADDR1 and ADDR0 pins are used for external PWM inputs to directly control the current output as described in External PWM Input PWM0 and PWM1.
If EEP_INTADDR is 0, the device uses EEP_DEVADDR[3] code together with external inputs on ADDR2, ADDR1 and ADDR0 as shown in Table 8-7 and ignore EEP_DEVADDR[2:0] code.
The address 0h to Fh can be used as slave address for up to 16 pieces of TPS929121-Q1 in same FlexWire bus. In broadcast mode, 0h must be used for all slave devices address. It is not allowed to have two TPS929121-Q1 sharing the same slave address either setting by internal EEPROM register EEP_DEVADDR or address pins configuration on ADDR2, ADDR1 and ADDR0.
| Address(HEX) | INTERNAL ADDRESS SETTING | EXTERNAL ADDRESS SETTING | ||||||
|---|---|---|---|---|---|---|---|---|
| BIT3 | BIT2 | BIT1 | BIT0 | BIT3 | BIT2 | BIT1 | BIT0 | |
| EEP_DEVADDR[3] | EEP_DEVADDR[2] | EEP_DEVADDR[1] | EEP_DEVADDR[0] | EEP_DEVADDR[3] | ADDR2 | ADDR1 | ADDR0 | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
| 2 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |
| 3 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
| 4 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
| 5 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 |
| 6 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 |
| 7 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
| 8 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 9 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
| A | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 |
| B | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
| C | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
| D | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
| E | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
| F | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
The TPS929121-Q1 has EEP_DEVADDR[3] bit set to 0 as default, however TPS929121A version has EEP_DEVADDR[3] bit set to 1 as default. It allows up to 16 pieces of TPS929121-Q1 on same FlexWire bus accessible through external configuration on ADDR2, ADDR1 and ADDR0 without burning the EEP_DEVADDR registers.