7.3.1 Adjusting the Output Voltage (VADJ)

The VADJ pin programs the output voltage of the TPSM84A21. The output voltage adjustment range is from 0.508 V to 1.35 V. The adjustment method requires the addition of R_SET connected between VADJ and AGND. If an R_SET resistor is not populated, the module will default to 0.508 V. The VS+ pin (pin 14) must be connected to VOUT. TI recommends to make the VS+ connection at the load for the best load regulation performance. The R_SET resistor must be connected directly between the VADJ pin (pin 15) and AGND (pin 16).

Equation 1 can be used to calculate the ideal R_SET resistor value for a given output voltage, V_OUT. Use Equation 2 to calculate the actual V_OUT for a given R_SET resistor. Table 1 lists the ideal R_SET resistor values for a number of common voltages. Table 1 also lists the closest E96 standard resistor values to the ideal R_SET values along with the actual output voltage and the set-point error when using the E96 resistor value. For the most accurate output voltage set-point it is best to use the ideal resistor value. The ideal resistor value may not be a standard value and may require two standard value resistors in series or parallel to obtain the desired output voltage.

Equation 1.

Equation 2.

7.3.2 Input and Output Capacitance

The TPSM84A21 requires no external input or output capacitance to operate. Internal to the TPSM84A21 there is 66.1 µF (nominal) of ceramic input capacitance. Additionally, internal to the TPSM84A21 there is 185 µF (nominal) of ceramic output capacitance.

Applications requiring additional ripple voltage reduction should add ceramic input and output capacitors directly at the VIN and VOUT pins of the device. Applications requiring improved transient response can also benefit by adding additonal ceramic or low-ESR bulk output capacitance. See the Capacitance section of the Electrical Characteristics table for more information when adding external input and output capacitors.

7.3.3 Transient Response

The exceptional transient response of the TPSM84A21 allows many applications to operate with little or no additional output capacitance. Figure 11 through Figure 14 show typical transient waveforms for the TPSM84A21.

7.3.3.1 Transient Response Waveforms

VIN = 12 V	VOUT = 0.8 V	Load Step = 5 A
	COUT = 0 µF	Slew Rate = 1 A/µs

Figure 11. Transient Response

VIN = 12 V	VOUT = 1.0 V	Load Step = 5 A
	COUT = 0 µF	Slew Rate = 1 A/µs

Figure 13. Transient Response

VIN = 12 V	VOUT = 0.8 V	Load Step = 5 A
	COUT = 300 µF	Slew Rate = 5 A/µs

Figure 12. Transient Response

VIN = 12 V	VOUT = 1.0 V	Load Step = 5 A
	COUT = 100 µF	Slew Rate = 5 A/µs

Figure 14. Transient Response

7.3.4 Oscillator Frequency

The oscillator frequency of this converter is set at 4 MHz. The per phase switching frequency of the converter is half the oscillator frequency, or 2 MHz per phase. The oscillator frequency is fixed internally.

During load transients, the internal control loop will momentarily change the switching frequency in order to meet the output voltage recovery.

7.3.5 External Clock Syncronization

An external clock can be connected to the SYNC pin. The external clock signal overrides the internal oscillator and is used as the system clock. This feature enables the user to synchronize the switching events to a master clock on their board. The internal phase locked loop (PLL) has been implemented to allow synchronization at frequencies between ±10% of the nominal oscillator frequency. This allows the user to easily switch between the internal oscillator mode and the external clock mode while converting power. Before the external clock is present or after it is removed, the device with default to the internal oscillator setting.

To implement the synchronization feature, connect a square wave clock signal to the SYNC pin with a duty cycle between 20% and 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The start of the switching cycle is synchronized to the rising edge of the SYNC pin. The device can be configured for operation in applications where both an internal oscillator mode and an external synchronization clock mode are needed. Before the external clock is present, the switching frequency of the device is set by the internal oscillator. When the external clock is present, the SYNC mode overrides the internal oscillator. The first time the SYNC pin is pulled above the SYNC high threshold (2 V), the device switches from the internal oscillator mode to the SYNC mode and the PLL starts to lock onto the frequency of the external clock. When the external SYNC clock is removed, the converter will transition back to the internal oscillator after 4 internal clock cycles.

7.3.6 Soft Start

The TPSM84A21 has a pre-programmed soft start time of 4.1 ms (typ). The soft start time is the time it takes for the output voltage to rise from zero volts to the voltage set by the R_SET resistor. Soft start is an important feature that limits inrush current and reduces the load on the input supply to this device. During soft start, the internal reference voltage is slowly ramped up to the internal reference voltage. This slowly increases the commanded output voltage of the converter and reduces the initial surge in current. During soft start PGOOD remains low, the PLL is not active, and output UVP/OVP faults are disabled.

7.3.7 Power Good (PGOOD)

The Power Good (PGOOD) pin is an open drain output. After startup, when the VADJ pin is typically between 95% and 105% of the internal voltage reference, the PGOOD pin pull-down is released and the pin floats. The recommended pull-up resistor value is between 10 kΩ and 100 kΩ to a voltage source of 5.5 V or less. For convenience, VG can be used as the pull-up voltage. The PGOOD is in a defined state once the VIN input voltage is greater than approximately 1.2 V, but with reduced current sinking capability. The PGOOD achieves full current sinking capability once the VIN input voltage is above the input UVLO. The PGOOD pin is pulled low when the VADJ pin voltage is typically lower than 95% or greater than 105% of the nominal internal reference voltage. The PGOOD pin is also pulled low if a fault is detected, the EN pin is pulled low, or the converter is performing its soft-start power up sequence.

7.3.8 Gate Driver (VG)

A linear regulator internal to the TPSM84A21 generates a 4.8 V internal supply rail on the VG pin. The input of the linear regulator comes from the VIN pin. The VG supply rail is used to power the internal gate drivers and is the input to another regulator that generates the internal supply rails used by the controller. To improve converter efficiency, an external 5 V supply is recommended to be connected to the VG pin, thereby overriding the internal 4.8 V regulator. This external supply must be between 5.0 V and 5.5 V and must be present before applying input voltage to the VIN pin. If not supplying an external voltage to this pin, leave this pin open.

7.3.9 Startup into Pre-biased Outputs

The TPSM84A21 prevents the low-side MOSFETs from discharging a pre-biased output. During pre-biased startup, the low-side MOSFETs do not turn on until after the high-side MOSFETs have started switching. The high-side MOSFETs do not start switching until the internal soft-start reference voltage exceeds the voltage at the VADJ pin.

7.3.10 Thermal Shutdown

The internal thermal shutdown fault is triggered if the junction temperature exceeds 135°C (typ). This interrupts regulation by making the output high impedance. The device reinitiates the power up sequence when the junction temperature drops below 115°C (typ).

7.3.11 Overcurrent Protection

For protection against load faults, the TPSM84A21 incorporates output overcurrent protection. Applying a load that exceeds the module's overcurrent threshold causes the output to shut down and PGOOD is pulled low. Following shut down, the module attempts to restart after a 32.8-ms hiccup interval counter has expired. This provides a hiccup response to an overcurrent condition. During this period, the average current flowing into the fault is significantly reduced which reduces power dissipation. Once the fault is removed, the module automatically recovers and returns to normal operation.

The TPSM84A21 overcurrent trip point is 15 A (typ) when the ILIM pin is left open. This provides enough margin for brief overshoots in inductor currents during a load transient while at the same time protecting against short circuits or other potentially catastrophic faults on the output. The overcurrent trip point can be reduced to 11.25 A (typ) by placing a 47 kΩ between the ILIM pin and PGND. Programming resistors with up to ±5% variation can be used. The current limit selection is latched in at power up and cannot be changed without cycling input power or the EN pin voltage.

7.3.12 Output Undervoltage/Overvoltage Protection

The device incorporates an output undervoltage/overvoltage protection (UVP/OVP) circuit to prevent damage to the load. This fault can be triggered during large, fast load transients if insufficient output capacitance is used. The UVP/OVP feature compares the VADJ pin voltage to internal thresholds. If the VADJ pin voltage is lower than 90% or greater than 110% of the nominal internal reference voltage, the module is turned off, a fault is triggered, and the PGOOD pin is pulled low. When the fault hiccup interval is complete, the module will attempt to restart.

7.3.13 Enable (EN)

The EN pin provides electrical on and off control of the TPSM84A21. Once the EN pin voltage exceeds the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the module stops switching and enters a low power state. There is no voltage hysteresis in the EN threshold. The rising and falling voltage thresholds occur at the same level. The EN pin has an internal pull-up current source, allowing the user to float the EN pin for enabling the device.

If an application requires controlling the EN pin, use an open drain/collector device or a suitable logic gate to interface with the pin. Figure 15 shows controlling the EN/UVLO pin using a MOSFET, Q1. Turning Q1 on, disables the device. Using a voltage superviser to control the EN pin allows control of the turn-on and turn-off of the device as opposed to relying on the ramp up or down of the input voltage source.

Figure 15. Enable Control

7.3.14 Undervoltage Lockout (UVLO)

The TPSM84A21 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage is below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 7.65 V(max) with a typical hysteresis of 250 mV.

If an application requires a higher UVLO threshold, the UVLO pin can be configured as shown in Figure 16. The value of R_UVLO1 and R_UVLO2 can be calculated using Equation 3 and Equation 4 or selected from Table 2. It is recommended to set the UVLO hysteresis of approximately 500mV in order to avoid repeated chatter during start up or shut down. Table 2 shows recommended R_UVLO1 and R_UVLO2 values for various VIN UVLO rising thresholds, with 500 mV of hysteresis.

Equation 3.

Equation 4.

Figure 16. Adjustable UVLO

7.4.1 Active Mode

The TPSM84A21 is in Active Mode when VIN is above the UVLO threshold and the EN/UVLO pin voltage is above the EN high threshold. The simplest way to enable the TPSM84A21 is to leave the EN/UVLO pin floating. This allows self start-up of the TPSM84A21 when the input voltage is above the UVLO threshold.

7.4.2 Light Load Operation

The TPSM84A21 operates in forced continuous conduction mode (FCCM) under light load conditions. When operating in FCCM, the switching frequency remains constant and the high side and low side MOSFETs are turned on and off in a complementary fashion allowing negative inductor current for part of the switching cycle.

7.4.3 Shutdown Mode

The EN/UVLO pin provides electrical ON and OFF control for the TPSM84A21. When the EN/UVLO pin voltage is below the EN threshold, the device is in shutdown mode. In shutdown mode the stand-by current is typically less than 50 μA. The TPSM84A21 also employs under voltage lock out protection. If VIN is below the UVLO level, the output of the regulator turns off.