7.3.1 Integer and Fractional Mode Selection

The PLL is designed to operate in either Integer mode or Fractional mode. If the desired local oscillator (LO) frequency is an integer multiple of the phase frequency detector (PFD) frequency, f_PFD, then Integer mode can be selected. The normalized in-band phase noise floor in Integer mode is lower than in Fractional mode. In Integer mode, the feedback divider is an exact integer, and the fraction is zero. While operating in Integer mode, the register bits corresponding to the fractional control are don’t care.

In Fractional mode, the feedback divider fractional portion is non-zero on average. With 25-bit fractional resolution, RF stepsize f_PFD/2²⁵ is less than 1 Hz with a f_PFD up to 33 MHz. The appropriate fractional control bits in the serial register must be programmed.

7.3.2 Description of PLL Structure

Figure 79. Block Diagram of the PLL Loop

The output frequency is given by Equation 1:

Equation 1.

The rate at which phase comparison occurs is f_REF/RDIV. In Integer mode, the fractional setting is ignored and Equation 2 is applied.

Equation 2.

The feedback divider block consists of a programmable RF divider, a prescaler divider, and an NF divider. The prescaler can be programmed as either a 4/5 or an 8/9 prescaler. The NF divider includes an A counter and an M counter.

7.3.3 Fractional Mode Setup

Optimal operation of the PLL in fractional mode requires several additional register settings. Recommended values are listed in Table 1. Optimal performance may require tuning the MOD_ORD, ISOURCE_SINK, and ISOURCE_TRIM values according to the chosen frequency band.

7.3.4 Selecting the VCO and VCO Frequency Control

To achieve a broad frequency tuning range, the TRF372017 includes four VCOs. Each VCO is connected to a bank of capacitors that determine its valid operating frequency. For any given frequency setting, the appropriate VCO and capacitor array must be selected.

The device contains logic that automatically selects the appropriate VCO and capacitor bank. Set bit EN_CAL to initiate the calibration algorithm. During the calibration process, the device selects a VCO and a capacitor state so that VTune matches the reference voltage set by VCO_CAL_REF_n. Accuracy of the tune is increased through bits CAL_ACC_n. Because a calibration begins immediately when EN_CAL is set, all registers must contain valid values before initiating calibration.

Calibration logic is driven by a CAL_CLK clock derived from the phase frequency detector frequency scaled according to the setting in CAL_CLK_SEL. Faster CAL_CLK frequency enables faster calibration, but the logic is limited to clock frequencies around 1 MHz. Table 2 provides suggested CAL_CLK_SEL scaling recommendations for several phase frequency detector frequencies. The flag R_SAT_ERR is evaluated during the calibration process to indicate calibration counter overflow errors, which occurs if CAL_CLK runs too fast. If R_SAT_ERR is set during a calibration, the resulting calibration is not valid and CAL_CLK_SEL must be used to slow the CAL_CLK. CAL_CLK frequencies should not be set to less than 0.1 MHz.

When VCOSEL_MODE is 0, the device automatically selects both the VCO and capacitor bank within 23 CAL_CLK cycles. When VCOSEL_MODE is 1, the device uses the VCO selected in VCO_SEL_0 and VCO_SEL_1 and automatically selects the capacitor array within 17 CAL_CLK cycles. The VCO and capacitor array settings resulting from calibration cannot be read from the VCO_SEL_n and VCO_TRIM_n bits in registers 2 and 7. They can only be read from register 0.

Automatic calibration can be disabled by setting CAL_BYPASS to 1. In this manual cal mode, the VCO is selected through register bits VCO_SEL_n, while the capacitor array is selected through register bits VCO_TRIM_n. Calibration modes are summarized in Table 3. After calibration is complete, the PLL is released from calibration mode to reach an analog lock.

During the calibration process, the TRF372017 scans through many frequencies. RF and LO outputs should be disabled until calibration is complete. At power up, the RF and LO output are disabled by default.

Once a calibration has been performed at a given frequency setting, the calibration is valid over all operating temperature conditions.

7.3.5 External VCO

An external LO or VCO signal may be applied. EN_EXTVCO powers the input buffer and selects the buffered external signal instead of an internal VCO. Dividers, the pfd, and the charge pump remain enabled and may be used to drive an external VCO. NEG_VCO must correspond to the gain of the external VCO.

7.3.6 VCO Test Mode

Setting VCO_TEST_MODE forces the currently selected VCO to the edge of its frequency range by disconnecting the charge pump input from the pfd and loop filter and forcing its output high or low. The upper or lower edge of the VCO range is selected through COUNT_MODE_MUX_SEL.

VCO_TEST_MODE also reports the value of a frequency counter in COUNT, which can be read back in register 0. COUNT reports the number of digital N divider cycles in the PLL, directly related to the period of fN, that occur during each CAL_CLK cycle. Counter operation is initiated through the bit EN_CAL.

7.3.7 Lock Detect

The lock detect signal is generated in the phase frequency detector by comparing the VCO target frequency against the VCO actual frequency. When the phase of the two compared frequencies remains aligned for several clock cycles, an internal signal goes high. The precision of this comparison is controlled through the LD_ANA_PREC bits. This internal signal is then averaged and compared against a reference voltage to generate the LD signal. The number of averages used is controlled through LD_DIG_PREC. Therefore, when the VCO is frequency locked, LD is high. When the VCO frequency is not locked, LD may pulse high or exhibit periodic behavior.

By default, the internal lock detect signal is driven on the LD terminal. Register bits MUX_CTRL_n can be used to control a mux to output other diagnostic signals on the LD output. The LD control signals are shown in Table 5.

7.3.8 Tx Divider

The Tx divider, illustrated in Figure 80, converts the differential output of the VCO into differential I and Q mixer components. The divide by 1 differential quadrature phases are provided through a polyphase. Divide by 2, 4, and 8 differential quadrature phases are provided through flip-flop dividers. Only one of the dividers operates at a time, and the appropriate output is selected by a mux. DIVn bits are controlled through TX_DIV_SELn.

TX_DIV_I determines the bias level for the divider blocks. The SPEEDUP control is used to bypass a stabilization resistor and reach the final bias level faster after a change in the divider selection. SPEEDUP should be disabled during normal operation.

Figure 80. Tx Divider

7.3.9 LO Divider

The LO divider is shown in Figure 81. It frequency divides the VCO output. Only one of the dividers operates at a time, and the appropriate output is selected by a mux. DIVn bits are controlled through LO_DIV_SELn. The output is buffered and provided on output pins LO_OUT_P and LO_OUT_N. The output level is controlled through BUFOUT_BIASn.

LO_DIV_I determines the bias level for the divider blocks. The SPEEDUP control is used to bypass a stabilization resistor and reach the final bias level faster after a change in the divider selection. SPEEDUP should be disabled during normal operation. Although SPEEDUP controls both the Tx and LO divider biases, the Tx and LO divider biases are generated independently.

Figure 81. LO Divider

7.3.10 Mixer

A diagram of the mixer is shown in Figure 82. The mixer is followed by a differential to single-ended converter and buffer for output.

Figure 82. Mixer

7.3.11 Disabling Outputs

RF frequency outputs are generated at the RFOUT and LO* terminals. Unused RF frequency outputs should be disabled to minimize power consumption and noise generation. Table 7 lists settings used to disable the outputs. Power-save mode can also be used to disable outputs.

7.3.12 Power Supply Distribution

Power supply distribution for the TRF372017 is shown in Figure 83. Proper isolation and filtering of the supplies is critical for low noise operation of the device. Each supply pin should be supplied with local decoupling capacitance and isolated with a ferrite bead. VCC_VCO2 is tolerant of 5-V supply voltages to permit additional supply filtering.

Figure 83. Power Supply Distribution

7.3.13 Carrier Feedthrough Cancellation

The structure of the baseband current DAC is shown in Figure 84. For each input pair, there is a programmable reference current. The reference current for each pair (I and Q) is identical and is programmed through the same register bits, but the reference current source itself is duplicated in the device for both I and Q inputs. This current can be set to change the total current flowing into the P and N nodes, which in turn changes the offset programmability range.

The reference current is then mirrored and multiplied before getting injected into the input node. The total mirrored current is routed into the two sides of the differential pair and routed according to eight programmable bits. As the 8-bit setting is changed, current is shifted from one side of the pair into the other side for each of the I and Q input pairs. In practical usage, the offset current routing distributes the adjustment for each side of the pair, while the reference current sets the range of adjustment. This effect can be seen in Figure 78, which shows that the gain of the current routing is greater when the reference current setting is higher. However the step size also increases with increase in range. Figure 78 shows the effect on common mode voltage of varying the DAC reference current. Adjustment register bits are shown in Table 8.

Offset adjustment may be provided by an external source, such as a DAC QMC block, for DC-coupled systems.

Figure 84. Block Diagram of the Programmable Current DAC

7.3.14 Internal Baseband Bias Voltage Generation

The TRF372017 has the ability to generate DC voltage levels for its baseband inputs internally. Register settings in the device allow the user to adjust common mode voltage of the I and Q signals separately. There are three adjustment factors for the baseband inputs. These are described in Table 9.

Each baseband input pair includes the circuitry depicted in Figure 85. The Vref set voltage impacts all four terminals: IP, IN, QP, and QN. The effect of changing the reference voltage is shown in Figure 77. Each node also includes a programmable current DAC that injects current into the positive and negative terminals of each input.

Figure 85. Block Diagram of the Baseband I Input Nodes

Table 10. Frequency Range Operation

7.4.1 Powersave Mode

Powersave mode can be used to put the device into a low power consumption mode. The PLL block remains active in Powersave mode, reducing the time required for start-up. However, the modulator, dividers, output buffers, and baseband common mode generation blocks are powered down. The SPI block remains active, and registers are addressable. Use the PS pin to activate powersave mode.

7.5.1 Serial Interface Programming Registers Definition

The TRF372017 features a 3-wire serial programming interface (SPI) that controls an internal 32-bit shift register. There are a total of 3 signals that must be applied: the clock (CLK, pin 47), the serial data (DATA, pin 46) and the latch enable (LE, pin 45). The TRF372017 has an additional pin (RDBK, pin 2) for read-back functionality. This pin is a digital pin and can be used to read-back values of different internal registers.

The DATA (DB0-DB31) is loaded LSB first and is read on the rising edge of the CLOCK. The LE is asynchronous to the CLOCK and at its rising edge the data in the shift register gets loaded onto the selected internal register. The 5 LSB of the Data field are the address bits to select the available internal registers.