ZHCS266F June 2011 – May 2017 TRF7960A
PRODUCTION DATA.
Table 6-21 describes the bit fields of the TX Timer High Byte Control register. This register sets timings.
Default Value: 0xC2, set at POR = H or EN = L and at each write to the ISO Control register
| BIT NO. | BIT NAME | FUNCTION | DESCRIPTION |
|---|---|---|---|
| B7 | tm_st1 | Timer start condition | tm_st1 = 0, tm_st0 = 0: beginning of TX SOF tm_st1 = 0, tm_st0 = 1: end of TX SOF tm_st1 = 1, tm_st0 = 0: beginning of RX SOF tm_st1 = 1, tm_st0 = 1: end of RX SOF |
| B6 | tm_st0 | Timer start condition | |
| B5 | tm_lengthD | Timer length MSB | See Table 6-22 for timer length description. |
| B4 | tm_lengthC | Timer length | |
| B3 | tm_lengthB | Timer length | |
| B2 | tm_lengthA | Timer length | |
| B1 | tm_length9 | Timer length | |
| B0 | tm_length8 | Timer length LSB |