米6体育平台手机版

SLLSFB2 April 2020 TUSB1146

PRODUCTION DATA.

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
AUXp or AUXn and SBU1 or SBU2
t_{AUX_PD}	Switch propagation delay			400	ps
t_{AUX_SW_OFF}	Switching time CTL1 to switch OFF. Not including TCTL1_DEBOUNCE.	Refer to Figure 23.		500	ns
t_{AUX_SW_ON}	Switching time CTL1 to switch ON	Refer to Figure 22.		500	ns
t_{AUX_INTRA}	Intra-pair output skew			100	ps
USB3.1 and DisplayPort Mode Transition Requirement GPIO Mode
t_{GP_USB_4DP}	Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa.	I2C_EN = 0; Refer to Figure 18.	4		µs
CTL1 and HPDIN
t_{CTL1_DEBOUNCE}	CTL1 and HPDIN debounce time when transitioning from H to L.		2	10	ms
I²C
f_SCL	I²C clock frequency			1	MHz
t_BUF	Bus free time between START and STOP conditions	Refer to Figure 17	0.5		µs
t_HDSTA	Hold time after repeated START condition. After this period, the first clock pulse is generated	Refer to Figure 17	0.26		µs
t_LOW	Low period of the I²C clock	Refer to Figure 17	0.5		µs
t_HIGH	High period of the I²C clock	Refer to Figure 17	0.26		µs
t_SUSTA	Setup time for a repeated START condition	Refer to Figure 17	0.26		µs
t_HDDAT	Data hold time	Refer to Figure 17	0		µs
t_SUDAT	Data setup time	Refer to Figure 17	50		ns
t_R	Rise time of both SDA and SCL signals	Refer to Figure 17		120	ns
t_F	Fall time of both SDA and SCL signals	Refer to Figure 17	20 × (V_(I2C)/5.5 V)	120	ns
t_SUSTO	Setup time for STOP condition	Refer to Figure 17	0.26		µs
C_b	Capacitive load for each bus line			150	pF