Figure 9-5 and Figure 9-6 shows the bench test waveforms for the design example shown in Figure 9-1 under these conditions: VCC = 5.0 V, VDD = 12 V, f_SW = 100 kHz, V_DC-Link = 400 V.

Channel 1 (Yellow): INA pin signal.

Channel 2 (Blue): INB pin signal.

Channel 3 (Pink): Gate-source signal on the high side power transistor.

Channel 4 (Green): Gate-source signal on the low side power transistor.

In Figure 9-5, INA and INB are sent complimentary 3.3-V, 20%/80% duty-cycle signals with 200ns deadtime. The gate drive signals on the power transistor have a 200-ns dead time with 400V high voltage on the DC-Link, shown in the measurement section of Figure 9-5. Note that with high voltage present, lower bandwidth differential probes are required, which limits the achievable accuracy of the measurement.

Figure 9-6 shows a zoomed-in version of the waveform of Figure 9-5, with measurements for propagation delay and deadtime. Importantly, the output waveform is measured between the power transistors’ gate and source pins, and is not measured directly from the driver's OUTA and OUTB pins.

Figure 9-5 Bench Test Waveform for INA/B and OUTA/B

Figure 9-6 Zoomed-In bench-test waveform