ZHCSHS5B February   2018  – February 2024 UCC21222

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety-Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Thermal Derating Curves
    12. 5.12 Typical Characteristics
  7. Parameter Measurement Information
    1. 6.1 Minimum Pulses
    2. 6.2 Propagation Delay and Pulse Width Distortion
    3. 6.3 Rising and Falling Time
    4. 6.4 Input and Disable Response Time
    5. 6.5 Programmable Dead Time
    6. 6.6 Power-Up UVLO Delay to OUTPUT
    7. 6.7 CMTI Testing
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21222
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead Time (DT) Pin
        1. 7.4.2.1 DT Pin Tied to VCCI or DT Pin Left Open
        2. 7.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Designing INA/INB Input Filter
        3. 8.2.2.3 Select Dead Time Resistor and Capacitor
        4. 8.2.2.4 Select External Bootstrap Diode and its Series Resistor
        5. 8.2.2.5 Gate Driver Output Resistor
        6. 8.2.2.6 Estimating Gate Driver Power Loss
        7. 8.2.2.7 Estimating Junction Temperature
        8. 8.2.2.8 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.8.1 Selecting a VCCI Capacitor
          2. 8.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.8.3 Select a VDDB Capacitor
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Component Placement Considerations
      2. 10.1.2 Grounding Considerations
      3. 10.1.3 High-Voltage Considerations
      4. 10.1.4 Thermal Considerations
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Connecting a Programming Resistor between DT and GND Pins

Program tDT by placing a resistor, RDT, between the DT pin and GND. The appropriate RDT value can be determined from:

Equation 1. GUID-A4B61FF0-E3A0-450A-B6D6-176517D74EDD-low.gif

where

  • tDT is the programmed dead time, in nanoseconds.
  • RDT is the value of resistance between DT pin and GND, in kilo-ohms.

The steady state voltage at the DT pin is about 0.8 V. RDT programs a small current at this pin, which sets the dead time. As the value of RDT increases, the current sourced by the DT pin decreases. The DT pin current will be less than 10 µA when RDT = 100 kΩ. For larger values of RDT, TI recommends placing RDT and a ceramic capacitor, 2.2 nF or greater, as close to the DT pin as possible to achieve greater noise immunity and better dead time matching between both channels.

The falling edge of an input signal initiates the programmed dead time for the other signal. The programmed dead time is the minimum enforced duration in which both outputs are held low by the driver. The outputs may also be held low for a duration greater than the programmed dead time, if the INA and INB signals include a dead time duration greater than the programmed minimum. If both inputs are high simultaneously, both outputs will immediately be set low. This feature is used to prevent shoot-through in half-bridge applications, and it does not affect the programmed dead time setting for normal operation. Various driver dead time logic operating conditions are illustrated and explained in Figure 7-4.

GUID-678434F2-9E60-47D6-90B5-E292C8D3BC11-low.gif Figure 7-4 Input and Output Logic Relationship with Input Signals

Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead time to OUTA. OUTA is allowed to go high after the programmed dead time.

Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed dead time to OUTB. OUTB is allowed to go high after the programmed dead time.

Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead time for OUTA. In this case, the input signal dead time is longer than the programmed dead time. When INA goes high after the duration of the input signal dead time, it immediately sets OUTA high.

Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead time to OUTB. In this case, the input signal dead time is longer than the programmed dead time. When INB goes high after the duration of the input signal dead time, it immediately sets OUTB high.

Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, OUTB is immediately pulled low. After some time OUTB goes low and assigns the programmed dead time to OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high.

Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, OUTA is immediately pulled low. After some time OUTA goes low and assigns the programmed dead time to OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.