ZHCSF55E
June 2016 – December 2021
UCC21520
PRODUCTION DATA
1
特性
2
应用
3
说明
4
Revision History
5
说明(续)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Power Ratings
7.6
Insulation Specifications
7.7
Safety-Related Certifications
7.8
Safety-Limiting Values
7.9
Electrical Characteristics
7.10
Switching Characteristics
7.11
Insulation Characteristics Curves
7.12
Typical Characteristics
8
Parameter Measurement Information
8.1
Propagation Delay and Pulse Width Distortion
8.2
Rising and Falling Time
8.3
Input and Disable Response Time
8.4
Programable Dead Time
8.5
Power-up UVLO Delay to OUTPUT
8.6
CMTI Testing
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
VDD, VCCI, and Undervoltage Lock Out (UVLO)
9.3.2
Input and Output Logic Table
9.3.3
Input Stage
9.3.4
Output Stage
9.3.5
Diode Structure in the UCC21520 and the UCC21520A
9.4
Device Functional Modes
9.4.1
Disable Pin
9.4.2
Programmable Dead-Time (DT) Pin
9.4.2.1
Tying the DT Pin to VCC
9.4.2.2
DT Pin Connected to a Programming Resistor between DT and GND Pins
9.4.2.3
41
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Designing INA/INB Input Filter
10.2.2.2
Select External Bootstrap Diode and its Series Resistor
10.2.2.3
Gate Driver Output Resistor
10.2.2.4
Gate to Source Resistor Selection
10.2.2.5
Estimate Gate Driver Power Loss
10.2.2.6
Estimating Junction Temperature
10.2.2.7
Selecting VCCI, VDDA/B Capacitor
10.2.2.7.1
Selecting a VCCI Capacitor
10.2.2.7.2
Selecting a VDDA (Bootstrap) Capacitor
10.2.2.7.3
Select a VDDB Capacitor
10.2.2.8
Dead Time Setting Guidelines
10.2.2.9
Application Circuits with Output Stage Negative Bias
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
第三方米6体育平台手机版_好二三四免责声明
13.2
Documentation Support
13.2.1
Related Documentation
13.3
Certifications
13.4
Receiving Notification of Documentation Updates
13.5
支持资源
13.6
Trademarks
13.7
Electrostatic Discharge Caution
13.8
术语表
14
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
DW|16
MSOI003I
散热焊盘机械数据 (封装 | 引脚)
DW|16
QFND505A
订购信息
zhcsf55e_oa
zhcsf55e_pm
1
特性
通用:双路低侧、双路高侧或半桥驱动器
工作温度范围:–40°C 至 +125°C
开关参数:
19ns 典型传播延迟
10ns 最小脉冲宽度
5ns 最大延迟匹配
6
ns 最大脉宽失真
共模瞬态抗扰度 (CMTI) 大于 100V/ns
浪涌抗扰度高达 12.8kV
隔离层寿命 > 40 年
4A 峰值拉电流、6A 峰值灌电流输出
TTL 和 CMOS 兼容输入
3V 至 18V 输入 VCCI 范围,可连接数字和模拟控制器
高达 25V 的 VDD 输出驱动电源
5V 和 8V VDD UVLO 选项
可通过编程的重叠和死区时间
抑制短于 5ns 的输入脉冲和噪声瞬态
电源定序快速禁用
业界通用的宽体 SOIC-16 (DW) 封装
安全相关认证:
符合 DIN V VDE V 0884-11:2017-01 标准的 8000V
PK
增强型隔离
符合 UL 1577 标准且长达 1 分钟的 5.7kV
RMS
隔离
获得 CSA 认证,符合 IEC 60950-1、IEC 62368-1、IEC 61010-1 和 IEC 60601-1 终端设备标准
获得 CQC 认证,符合 GB4943.1-2011 标准
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