ZHCSF55E June 2016 – December 2021 UCC21520
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 说明（续）
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Power Ratings
- 7.6 Insulation Specifications
- 7.7 Safety-Related Certifications
- 7.8 Safety-Limiting Values
- 7.9 Electrical Characteristics
- 7.10 Switching Characteristics
- 7.11 Insulation Characteristics Curves
- 7.12 Typical Characteristics
- 8 Parameter Measurement Information
- 9 Detailed Description
-
10Application and Implementation
- 10.1 Application Information
- 10.2
Typical Application
- 10.2.1 Design Requirements
- 10.2.2
Detailed Design Procedure
- 10.2.2.1 Designing INA/INB Input Filter
- 10.2.2.2 Select External Bootstrap Diode and its Series Resistor
- 10.2.2.3 Gate Driver Output Resistor
- 10.2.2.4 Gate to Source Resistor Selection
- 10.2.2.5 Estimate Gate Driver Power Loss
- 10.2.2.6 Estimating Junction Temperature
- 10.2.2.7 Selecting VCCI, VDDA/B Capacitor
- 10.2.2.8 Dead Time Setting Guidelines
- 10.2.2.9 Application Circuits with Output Stage Negative Bias
- 10.2.3 Application Curves
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
9.4.2.3
The steady state voltage at DT pin is around 0.8 V, and the DT pin current will be less than 10uA when RDT=100kΩ. When using RDT> 5kΩ, it is recommended to parallel a ceramic capacitor, 2.2nF or above, close to the chip with RDT to achieve better noise immunity and better dead time matching between two channels. It is not recommended to leave the DT pin floating.
An input signal’s falling edge activates the programmed dead time for the other signal. The output signals’ dead time is always set to the longer of either the driver’s programmed dead time or the input signal’s own dead time. If both inputs are high simultaneously, both outputs will immediately be set low. This feature is used to prevent shoot-through, and it doesn’t affect the programmed dead time setting for normal operation. Various driver dead time logic operating conditions are illustrated and explained in Figure 9-4:
Figure 9-4 Input and Output Logic Relationship With Input SignalsCondition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead time to OUTA. OUTA is allowed to go high after the programmed dead time.
Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed dead time to OUTB. OUTB is allowed to go high after the programmed dead time.
Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead time for OUTA. In this case, the input signal’s own dead time is longer than the programmed dead time. Thus, when INA goes high, it immediately sets OUTA high.
Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead time to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, it immediately sets OUTB high.
Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high.
Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.