ZHCSIL2C July 2018 – March 2022 UCC24624
PRODUCTION DATA
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | VG1 | O | VG1 is the controlled MOSFET gate drive for channel 1. Connect VG1 to the gate of the channel 1 SR MOSFET through a small series resistor using short PCB traces to achieve optimal switching performance. The VG1 output can achieve 1.5-A peak source current, and 4-A peak sink current when connected to a large N-channel power MOSFET. |
| 2 | PGND | - | PGND is the power return pin of the UCC24624. The IC bias current and high peak current from the gate drivers return to this pin. Short PCB traces and the ceramic bypass capacitor are required to minimize the high slew rate current impacts to the IC operation. The PGND should be connected directly to the SR MOSFET source pins. |
| 3 | REG | O | REG is the internal linear regulator output and the device's internal bias pin. An internal linear regulator from VDD to REG generates a well-regulated 11-V voltage. TI recommends putting a 2.2-μF bypass capacitor from REG pin to PGND pin. Before REG pin reaches VREGON, one of the drain voltages (VD1 or VD2) must switch above VTHARM. |
| 4 | VD1 | I | VD1 is the channel 1 SR MOSFET drain voltage sensing input. Connect this pin to channel 1 SR MOSFET drain pin. The layout should avoid the VD1 pin trace sharing the power path to minimize the impacts of parasitic inductance. |
| 5 | VSS | I | VSS is used to sense the voltage drop across the SR MOSFETs. Since both channels are sharing the same VSS pin to sense the MOSFET voltage, special attention is required. The layout should avoid the VSS pin trace sharing the power path to minimize the impacts of parasitic inductor. See Section 11.2 for more details. A resistor can be added between VSS pin and SR MOSFET source pins to adjust the SR turn-off threshold if it is needed. |
| 6 | VD2 | I | VD2 is the channel 2 SR MOSFET drain voltage sensing input. Connect this pin to channel 2 SR MOSFET drain pin. The layout must avoid the VD2 pin trace sharing the power path to minimize the impacts of parasitic inductance. |
| 7 | VDD | I | VDD is the internal linear regulator input. Connect this pin to the output voltage when the output voltage is less than 24.75 V. When the output voltage is higher than 24.75 V, add a series resistor between LLC output voltage and the VDD pin to limit the internal clamping circuit current. |
| 8 | VG2 | O | VG2 is the controlled MOSFET gate drive for channel 2. Connect VG2 to the gate of the channel 2 MOSFET through a small series resistor using short PCB traces to achieve optimal switching performance. The VG2 output can achieve 1.5-A peak source current and 4-A peak sink current when connected to a large N-channel power MOSFET. |