ZHCSC00C December   2013  – September 2024 UCC27532-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. 说明(续)
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD Undervoltage Lockout
      2. 7.3.2 Input Stage
      3. 7.3.3 Enable Function
      4. 7.3.4 Output Stage
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Driving IGBT Without Negative Bias
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input-to-Output Configuration
          2. 8.2.1.2.2 Input Threshold Type
          3. 8.2.1.2.3 VDD Bias Supply Voltage
          4. 8.2.1.2.4 Peak Source and Sink Currents
          5. 8.2.1.2.5 Enable and Disable Function
          6. 8.2.1.2.6 Propagation Delay
          7. 8.2.1.2.7 Power Dissipation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Driving IGBT With 13-V Negative Turnoff Bias
      3. 8.2.3 Using UCC27532-Q1 Drivers in an Inverter
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Consideration
  12. 11Device and Documentation Support
    1. 11.1 第三方米6体育平台手机版_好二三四免责声明
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

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订购信息

Electrical Characteristics

Unless otherwise noted, VDD = 18 V, TA = TJ = –40°C to 140°C, IN switching from 0 V to VDD, 1-µF capacitor from VDD to GND, ƒ = 100 kHz. Currents are positive into and negative out of the specified terminal. OUTH and OUTL are tied together. Typical condition specifications are at 25°C.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
BIAS CURRENTS
IDDoffStartup current, VDD = 7IN, EN = VDD100240350μA
IN, EN = GND100250350
UNDERVOLTAGE LOCKOUT (UVLO)
VONSupply start threshold88.99.8V
VOFFMinimum operating voltage after supply start7.38.29.1V
VDD_HSupply voltage hysteresis0.7V
INPUT (IN)
VIN_HInput signal high thresholdVDD = 16V, Output high8.89.410V
VIN_LInput signal low thresholdVDD = 16V, Output low6.77.37.9V
VIN_HYSInput signal hysteresisVDD = 16V2.1V
ENABLE (EN)
VEN_HEnable signal high thresholdVDD = 16V, Output high1.71.92.1V
VEN_LEnable signal low thresholdVDD = 16V, Output low0.811.2V
VEN_HYSEnable signal hysteresisVDD = 16V0.9V
OUTPUTS (OUTH/OUTL)
ISRC/SNKSource peak current (OUTH)/ sink peak current (OUTL)(1)CLOAD = 0.22 µF, ƒ = 1 kHz–2.5 / 5A
VOHOUTH, high voltageIOUTH = –10 mAVDD –0.2VDD –0.12VDD –0.07V
VOLOUTL, low voltageIOUTL = 100 mA0.0650.125V
ROHOUTH, pullup resistance(1)TA = 25°C, IOUT = -10 mA111212.5
TA = –40°C to 140°C, IOUT = -10 mA71220
ROLOUTL, pulldown resistanceTA = 25°C, IOUT = 100 mA0.450.650.85
TA = –40°C to 140°C, IOUT = 100 mA0.30.651.25
Output pullup resistance here is a DC measurement that measures resistance of PMOS structure only, not N-channel structure. The effective dynamic pullup resistance is 3 × ROL.