ZHCSC00C December   2013  – September 2024 UCC27532-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 说明（续）
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD Undervoltage Lockout
      2. 7.3.2 Input Stage
      3. 7.3.3 Enable Function
      4. 7.3.4 Output Stage
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Driving IGBT Without Negative Bias
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input-to-Output Configuration
          2. 8.2.1.2.2 Input Threshold Type
          3. 8.2.1.2.3 VDD Bias Supply Voltage
          4. 8.2.1.2.4 Peak Source and Sink Currents
          5. 8.2.1.2.5 Enable and Disable Function
          6. 8.2.1.2.6 Propagation Delay
          7. 8.2.1.2.7 Power Dissipation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Driving IGBT With 13-V Negative Turnoff Bias
      3. 8.2.3 Using UCC27532-Q1 Drivers in an Inverter
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Consideration
  12. 11Device and Documentation Support
    1. 11.1 第三方米6体育平台手机版_好二三四免责声明
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

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6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)(1)(2)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tRRise timeCLOAD = 1.8 nF15ns
tFFall timeCLOAD = 1.8 nF7ns
tD1Turnon propagation delayCLOAD = 1.8 nF, IN = 0 V to VDD1726ns
tD2Turnoff propagation delayCLOAD = 1.8 nF, IN = VDD to 0 V1726ns
(1) Ensured by design and tested during characterization. Not production tested.
(2) See Figure 6-1.
UCC27532-Q1 Timing Diagram: (OUTH Tied To OUTL) Input = IN, Output = OUT (EN = VDD) Or Input = EN, Output = OUT (IN = VDD) Figure 6-1 Timing Diagram: (OUTH Tied To OUTL) Input = IN, Output = OUT (EN = VDD) Or Input = EN, Output = OUT (IN = VDD)
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