5.1.1 VDD (Device Bias Voltage Supply)

The VDD pin connects to a by-pass capacitor to ground. The turn-on UVLO threshold is 21 V and turn-off UVLO threshold is 7.7 V with an available operating range up to 35 V on VDD. The typical USB charging specification requires the output current to operate in Constant-Current mode from 5 V down to at least 2 V, which is easily achieved with a nominal V_VDD of approximately 20 V. The additional VDD headroom up to 35 V allows for V_VDD to rise due to the leakage energy delivered to the VDD capacitor during high-load conditions.

5.1.2 GND (Ground)

UCC28730 has a single ground reference external to the device for the gate-drive current and analog signal reference. Place the VDD-bypass capacitor close to GND and VDD with short traces to minimize noise on the VS and CS signal pins.

5.1.3 HV (High Voltage Startup)

The HV pin connects directly to the bulk capacitor to provide startup current to the VDD capacitor. The typical startup current is approximately 250 µA which provides fast charging of the VDD capacitor. The internal HV startup device is active until V_VDD exceeds the turn-on UVLO threshold of 21 V at which time the HV startup device turns off. In the off state the HV leakage current is very low to minimize stand-by losses of the controller. When V_VDD falls below the 7.7-V UVLO turn-off threshold the HV startup device turns on.

5.1.4 DRV (Gate Drive)

The DRV pin connects to the MOSFET gate pin, usually through a series resistor. The gate driver provides a gate-drive signal limited to 14 V. The turn-on characteristic of the driver is a 29-mA current source which limits the turn-on dv/dt of the MOSFET drain and reduces the leading-edge current spike, while still providing a gate-drive current to overcome the Miller plateau. The gate-drive turn-off current is determined by the R_DS(on) of the low-side driver and any external gate drive resistance. Adding external gate resistance reduces the MOSFET drain turn-off dv/dt, if necessary. Such resistance value is generally higher than the typical 10 Ω commonly used to damp resonance. However, calculation of the external resistance value to achieve a specific dv/dt involves MOSFET parameters beyond the scope of this datasheet.

5.1.5 CBC (Cable Compensation)

The cable compensation pin is connected to a resistor to ground to program the amount of output voltage compensation needed to offset cable resistance. The cable compensation circuit generates a 0 to 3.13-V voltage level on the CBC pin corresponding to 0 A to I_OCC maximum output current. The resistance selected on the CBC pin programs a current mirror that is summed into the VS feedback divider therefore increasing the regulation voltage as I_OUT increases. There is an internal series resistance of 28 kΩ to the CBC pin which sets a maximum cable compensation for a 5-V output to approximately 400 mV when CBC is shorted to ground. The CBC resistance value can be determined using Equation 1.

Equation 1.

where

• V_CBC(max) is the maximum voltage at the cable compensation pin at the maximum converter output current (see Electrical Characteristics),
• V_OCV is the regulated output voltage,
• V_F is the diode forward voltage,
• V_VSR is the CV regulating level at the VS input (see Electrical Characteristics),
• V_OCBC is the target cable compensation voltage at the output terminals.

Note that the cable compensation does not change the overvoltage protection (OVP) threshold, V_OVP (see Electrical Characteristics), so the operating margin to OVP is less when cable compensation is used.

5.1.6 VS (Voltage Sense)

The VS pin connects to a resistor-divider from the auxiliary winding to ground and is used to sense input voltage, output voltage, event timing, and Wait-state wake-up signaling. The auxiliary voltage waveform is sampled at the end of the transformer secondary current demagnetization time to provide an accurate representation of the output voltage. The waveform on the VS pin determines the timing information to achieve valley-switching, and the timing to control the duty-cycle of the transformer secondary current when in Constant-Current Mode. Avoid placing a filter capacitor on this input which interferes with accurate sensing of this waveform.

During the MOSFET on-time, this pin also senses VS current generated through R_S1 by the reflected bulk-capacitor voltage to provide for AC-input Run and Stop thresholds, and to compensate the current-sense threshold across the AC-input range. For the AC-input Run/Stop function, the Run threshold on VS is 225 µA and the Stop threshold is 80 µA.

At the end of off-time demagnetization, the reflected output voltage is sampled at this pin to provide regulation and overvoltage protection. The values for the auxiliary voltage-divider upper-resistor, R_S1, and lower-resistor, R_S2, are determined by Equation 2 and Equation 3.

Equation 2.

where

• V_IN(run) is the target AC RMS voltage to enable turn-on of the controller (Run) (in case of DC input, leave out the √2 term in the equation),
• I_VSL(run) is the Run-threshold for the current pulled out of the VS pin during the switch on-time (see Electrical Characteristics),
• N_PA is the transformer primary-to-auxiliary turns-ratio.

Equation 3.

where

• V_OCV is the converter regulated output voltage,
• V_F is the output rectifier forward drop at near-zero current,
• N_AS is the transformer auxiliary-to-secondary turns-ratio,
• R_S1 is the VS divider high-side resistance,
• V_VSR is the CV regulating level at the VS input (see Electrical Characteristics).

When the UCC28730 is operating in the Wait state, the VS input is receptive to a wake-up signal superimposed upon the auxiliary winding waveform after the waveform meets either of two qualifying conditions. A high-level wake-up signal is considered to be detected if the amplitude at the VS input exceeds V_WU(high) (2 V) provided that any voltage at VS has been continuously below V_WU(high) for the wake-up qualification delay t_WDLY (8.5 us) after the demagnetization interval. A low-level wake-up signal is considered to be detected if the amplitude at the VS input exceeds V_WU(low) (57 mV) provided that any voltage at VS has been continuously below V_WU(low) for the wake-up qualification delay t_WDLY (8.5 us) after the demagnetization interval. The high-level threshold accommodates signals generated by a low-impedance secondary-side driver while the low-level threshold detects signals generated by a high-impedance driver.

5.1.7 CS (Current Sense)

The current-sense pin connects to a series resistor (R_LC) to the current-sense resistor (R_CS). The maximum current-sense threshold (V_CST(max)) is approximately 0.74 V for I_PP(max) and minimum current-sense threshold (V_CST(min)) is approximately 0.25 V for I_PP(min). R_LC provides the function of feed-forward line compensation to eliminate changes in I_PP with input voltage due to the propagation delay of the internal comparator and MOSFET turn-off time. An internal leading-edge blanking time of 225 ns eliminates sensitivity to the MOSFET turn-on current spike. It should not be necessary to place a bypass capacitor on the CS pin. The target output current in constant-current (CC) regulation determines the value of R_CS. The values of R_CS and R_LC are calculated by Equation 4 and Equation 5. The term V_CCR is the product of the demagnetization constant, 0.432, and V_CST(max). V_CCR is held to a tighter accuracy than either of its constituent terms. The term η_XFMR accounts for the energy stored in the transformer but not delivered to the secondary. This term includes transformer resistance and core loss, bias power, and primary-to-secondary leakage ratio.

Example: With a transformer core and winding loss of 5%, primary-to-secondary leakage inductance of 3.5%, and bias-power to output-power ratio of 0.5%, the η_XFMR value at full-power is: 1 - 0.05 - 0.035 - 0.005 = 0.91.

Equation 4.

where

• V_CCR is a constant-current regulation factor (see Electrical Characteristics),
• N_PS is the transformer primary-to-secondary turns-ratio, (a ratio of 13 to 15 is typical for a 5-V output),
• I_OCC is the target output current in constant-current regulation,
• η_XFMR is the transformer efficiency at full-power output.

Equation 5.

where

• K_LC is a current-scaling constant for line compensation (see Electrical Characteristics),
• R_S1 is the VS pin high-side resistor value,
• R_CS is the current-sense resistor value,
• N_PA is the transformer primary-to-auxiliary turns-ratio,
• t_D is the total current-sense delay consisting of MOSFET turn-off delay, plus approximately 50-ns internal delay,
• L_P is the transformer primary inductance.