8.3.1 VDD (Device Voltage Supply)

The VDD terminal is connected to a bypass capacitor to ground and typically to a rectifier diode connected to the auxiliary winding. The VDD turn on UVLO threshold is 9.5 V (VDD_ON typical) and turn off UVLO threshold is 6.5 V (VDD_OFF typical). The terminal is provided with an internal clamp that prevents the voltage from exceeding the absolute maximum rating of the terminal. The internal clamp cannot absorb currents higher than 10 mA (see I_VDD(clp) in Absolute Maximum Ratings), to avoid damaging the device, when the clamp flowing current exceeds 6 mA (I_{DDCLP_OC} typical) the device stops switching. The VDD terminal operating range is then from 7 V (VDD_OFF maximum) up to 26 V (VDD_CLAMP minimum). The USB charging specification requires that the output current operates in constant current mode from 5 V to a minimum of 2 V; this is easily achieved with a nominal VDD of approximately 17 V. Set N_AS (auxiliary-to-secondary windings turn ratio) to 17 V / (V_OUT + V_F) where V_F is the voltage drop on the output diode at low current. The additional VDD headroom up to the clamp allows for VDD to rise due to the leakage energy delivered to the VDD in high-load conditions.

Figure 13. VDD Current Consumption

8.3.2 GND (Ground)

The device is provided with three terminals, shorted together, that are used as external ground reference to the controller for analog signal reference. The three terminals function to pull out the heat caused by the power dissipation of the internal power FET. Place the VDD bypass capacitor close to GND and VDD with short traces to minimize noise on the VS and IPK signal terminals.

8.3.3 VS (Voltage Sense)

The VS terminal is connected to a resistor divider from the auxiliary winding to ground. The VS terminal provides three functions.

1. It provides output voltage information to the voltage control Loop. The output voltage feedback information is sampled at the end of the transformer secondary current demagnetization time to provide an accurate representation of the output voltage.
2. It also provides timing information to achieve valley switching and the duty cycle of the secondary transformer current is determined by the waveform on the VS terminal.
3. It samples the bulk capacitor input voltage providing under-voltage shutdown.

The data provided in 1) and 2) are sensed during the MOSFET off-time; 3) is performed during the MOSFET on-time when the auxiliary-winding voltage is negative.

During MOSFET on-time, the voltage on VS terminal is clamped to GND and through the resistance R_S1 connected between the auxiliary winding and VS. During the on-time, the current sourced from the VS terminal is sensed by the device. For the under-voltage function, the enable threshold on VS current is 210 μA and the disable threshold is 75 μA.

The resistor values for R_S1 and R_S2 can be determined by the equations below.

Equation 1.

where

Equation 2.

where

8.3.4 IPK (Set the Maximum DRAIN Current Peak)

A resistance (R_IPK) connected between IPK terminal and GND sets the maximum value of the power FET peak current. A current, I_SENSE, proportional to the power FET current comes out from the IPK terminal during power FET on time.

Equation 3.

where

The voltage across R_IPK is fed to the PWM comparator and established to switch off the power FET according to the following equation:

Equation 4.

where

If the terminal is shorted to GND (R_IPK = 0) the peak current is automatically set to 600 mA (I_{D_PEAK(max)}).

A test is performed at device start up to check whether the IPK terminal is shorted to GND or the R_IPK is present. If R_IPK is less than R_{IPK_SHORT} (maximum), the device interprets it as a short (R_IPK = 0) and the DRAIN peak current is set to I_{D_PEAK(max)}. Otherwise, if R_IPK is greater than R_IPK(min) (minimum), the device sets the peak current DRAIN according to the previous equation. A value of R_IPK that is in between the before said values, is not allowed since the value of the peak current may be selected using anyone of the two sense resistances: the internal sense resistance and R_IPK.

8.3.5 DRAIN

The DRAIN terminal is connected to the DRAIN of the internal power FET. This terminal also provides current to the high voltage current source at start up.

8.4.1 Primary-Side Voltage Regulation

Figure 14 illustrates a flyback converter. The voltage regulation blocks of the device are shown. The power train operation is the same as any DCM flyback circuit but accurate output voltage and current sensing is the key to primary side control.

Figure 14. Voltage Loop Block Diagram

In primary-side control, the output voltage is sensed by the auxiliary winding during the transfer of transformer energy to the secondary. Figure 15 shows the down slope representing a decreasing total rectifier V_F and the secondary winding resistance voltage drop as the secondary current decreases to 0 A. To achieve an accurate representation of the secondary output voltage on the auxiliary winding, the Discriminator Block (Figure 14) reliably ignores the leakage inductance reset and ring, continuously samples the auxiliary voltage during the down slope after the ringing is diminished, and captures the error signal at the time the secondary winding reaches 0 current. The internal reference on VS is 4 V; the resistor divider is selected as outlined in the VS terminal description.

Figure 15. Auxiliary Winding Voltage

The UCC28910 VS signal Discriminator Block (Figure 14) ensures accurate sampling time for an accurate sample of the output voltage from the auxiliary winding. There are however some details of the auxiliary winding signal to ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any subsequent leakage inductance ring. Refer to Figure 16 for a detailed illustration of waveform criteria to ensure a reliable sample on the VS terminal. The first detail to examine is the duration of the leakage inductance reset pedestal, t_{LK_RESET}. Since this can mimic the waveform of the secondary current decay, followed by a sharp down-slope, it is important to keep the leakage reset time less than 500 ns for I_DRAIN minimum, and less than 1.5 μs for I_DRAIN maximum. The second detail is the amplitude of ringing on the auxiliary winding waveform (V_AUX) following t_{LK_RESET}. The peak-to-peak voltage at the VS terminal should be less than approximately 100 mV_p-p at least 200 ns before the end of the demagnetization time, t_DMAG. If there is a concern with excessive ringing, it usually occurs during light or no-load conditions, when t_DMAG is at the minimum. The tolerable ripple on VS is scaled up to the auxiliary winding voltage by R_S1 and R_S2, and is equal to 100 (R_S1 + R_S2) / R_S2 mV.

Figure 16. VS Voltage

During voltage regulation, the controller operates in frequency modulation mode and amplitude modulation mode. The internal operating frequency limits of the controller are 115 kHz maximum and 420 Hz minimum. The transformer primary inductance and turns ratio sets the maximum operating frequency of the converter. The output preload resistor and efficiency at low power determines the converter minimum operating frequency. There is no external compensation required for the UCC28910 device.

8.4.2 Primary-Side Current Regulation

Timing information at the VS terminal and the primary current information allow accurate regulation of the secondary average current. The control law dictates that as power is increased in CV regulation and approaching CC regulation the primary-peak current is at I_{D_PK(max)} = V_CSTE(max) / R_IPK. Referring to Figure 17, the primary-peak current, turns ratio, secondary demagnetization time (t_DMAG), and switching period (t_SW) establish the secondary average output current. When the average output current reaches the regulation reference in the current control block, the controller operates in frequency modulation mode to control the output current at any output voltage at or below the voltage regulation target as long as the aux winding can keep VDD above the VDD UVLO threshold (VDD_OFF).

Figure 17. Output Current Estimation

Figure 18. Target Output V-I Characteristic

K_CC is defined as the maximum value of the secondary-side conduction duty cycle. It is set internally by the UCC28910 and occurs during constant current control mode.

Figure 19. Output Current Control Loop Block Diagram

8.4.3 Voltage Feed Forward Compensation

During normal operation the on-time is determined by sensing the power FET current and switching off the power FET as this current reaches a threshold fixed by the feedback loop according to the load condition. The power FET is not immediately turned off and its current, that is also the primary winding current, continues to rise for some time during the propagation delay (t_DELAY in Figure 20). Keeping the reference for the PWM comparator constant, the value of the primary winding peak current depends on the slope of the primary winding current and t_DELAY.

Figure 20. Propagation Delay Effect on the Primary Current Peak

Equation 5.

Equation 6.

The current loop estimates the output current assuming the primary winding peak current is equal to the I_{PK_TARGET} and compares this estimated current with a reference to obtain the current regulation. Considering, I_{D_PEAK} is different from I_{D_PEAK_TARGET} (see Figure 20) we need to compensate the effect of the propagation delay. The UCC28910 incorporates fully integrated propagation delay compensation that modifies the switching frequency keeping the output current constant during (CC) Constant Current Mode operation. This function is integrated in the controller and requires no external components. This feature keeps the output current constant despite input voltage variations and primary inductance value spread.

8.4.4 Control Law

During voltage regulation, the device operates in switching frequency modulation mode and primary current peak amplitude modulation mode. The internal operating frequency limits of the device are f_SW(max) and f_SW(min). The transformer primary inductance and primary-peak current chosen sets the maximum operating frequency of the converter. The output preload resistor and efficiency at low power determines the converter minimum operating frequency. During constant current regulation the device operates only in frequency modulation mode reducing the switching frequency as the output voltage decreases. Figure 21 shows how the primary peak current and the switching frequency change with respect to changes in load.

Figure 21. Control Law Profile

8.4.5 Valley Switching

The UCC28910 utilizes valley switching to reduce switching losses in the MOSFET and minimize the turn on FET current spike. The UCC28910 operates in valley switching in almost all load conditions until the V_DS ringing is diminished. By switching at the lowest V_DS voltage the MOSFET turn on dV / dt is minimized which is a benefit to reduce EMI.

Referring to Figure 22, the UCC28910 operates in a valley skipping mode in most load conditions to maintain an accurate voltage regulation point and still switch on the lowest available V_DS voltage.

Figure 22. Valley Skipping

Valley switching is maintained during constant current regulation to provide improved efficiency and EMI benefits in constant current operation.

In very light-load or no-load condition the V_DS ringing is very low and not easy to detect, moreover with very low ringing amplitude there would be no benefit in valley switching so in this condition the valley switching is disabled (see Figure 23).

Figure 23. Valley Switching Disable at Light Load

8.4.6 Startup Operation

UCC28910 is provided with a high-voltage current source, connected between the DRAIN terminal and the VDD terminal; this current source is activated when a voltage is applied on DRAIN terminal. The current source charges the capacitor connected between VDD and GND increasing the VDD voltage. As VDD exceeds VDD_ON the current source is turned off and the controller internal logic is activated and the device starts switching. If the VDD voltage falls below the VDD_OFF threshold, or a fault condition is detected, the controller stops operation and its current consumption is reduced to I_START or I_FAULT. The high-voltage current source is turned on again when VDD voltage goes below VDD_HV(on) (see Figure 11 for reference).

The initial three cycles are limited to I_{D_PEAK(max)} / 3. This allows sensing any input or output faults with minimal power delivery. After the initial three cycles at I_{D_PEAK(max)} / 3, the controller responds to the condition dictated by the control law.

Figure 24. Start Up and Auto Re-Start Operation

The converter remains in DCM during charging of the output capacitor(s), and operates in constant current mode until the output voltage is in regulation.

To avoid high-power dissipation inside the device, such as in the event that VDD is accidentally shorted to GND, the current provided by the high-voltage current source is reduced (I_CH1) until VDD < 1 V (typical).

8.4.7 Fault Protection

There is comprehensive fault protection incorporated into the UCC28910. Protection functions include:

• Output Over-Voltage Fault
• Input Under-Voltage Fault
• Internal Over-Temperature Fault
• Primary Over-Current Fault
• Maximum t_ON Fault
• VDD Clamp Over Current