There are a few ways to enable or disable the UCC28C5x-Q1 devices, depending on which type of restart is required. The two basic techniques use external transistors to either pull the error amplifier output low (< 2 V_BE) or pull the current sense input high (> 1.1 V). Application of the disable signal causes the output of the PWM comparator to be high. The PWM latch is reset dominant so that the output remains low until the next clock cycle after the shutdown condition at the COMP or CS pin is removed. Another choice for restart without a soft start is to pull the current sense input above the cycle-by-cycle current limiting threshold. A logic level P-channel FET from the reference voltage to the current sense input can be used.

Figure 8-7 Disable Circuit