During high-voltage (HV) startup from V_IN, capacitor C12 must hold the VDD voltage above the UVLO turn-off threshold until the AUX voltage rises high enough to forward bias D12. If the value of C12 is not high enough the VDD voltage will decay below the UVLO turn-off threshold and the converter will prematurely stop switching. The controller will continuously cycle on-and-off as the VDD voltage transitions between UVLO turn-on and UVLO turn-off. One of the most common issues seen with new designs is the VDD capacitor value is too low and “there's no output voltage” or "it's not starting" is reported.

First, estimate a total HV soft start time, t_SS. This estimate must include: (1) time for the COMP voltage to rise from 0 V to the PWM switching threshold (COMP to CS offset, 1.15 V_TYP), and (2) time for the AUX voltage (on C13) to rise from 0 V until it forward biases D12. Typical values are 1-2 ms for the COMP rise time and 10-14 ms for the AUX rise time. Calculate the VDD capacitor value with the following equation

Using I_{VDD_MAX} = 2 mA, f_SW = 42.5 kHz, Q_GATE = 11 nC, t_SS = 14 ms (2ms + 12ms),

VDD_ON = 17.6 V, and VDD_OFF = 14.5 V results in

Allowing ±20% initial capacitor tolerance and another 20% for endurance (life, temperature, etc.) means the VDD bulk capacitor must be at least 19.5 µF. Select the next higher standard capacitor value, 22 µF. This capacitor should be rated to at least the ABS MAX voltage of the VDD pin, 30 V.

The electrolytic bulk capacitor (C12) should be located relatively close to the VDD pin. On the other hand, the high-frequency bypass capacitor, C18, must be a ceramic type and be physically placed and grounded as close as possible to the VDD pin. A 1.0 μF, X7R capacitor is recommended for the high-frequency decoupling. To offset the effects of DC-bias, this capacitor must be rated to about 2x the expected VDD voltage (≥35V)