During the system start-up, VDD voltage starts to rise from 0 V. Before the VDD voltage reaches its corresponding turnon threshold, thedeviceis operating in UVLO mode. In this mode, the VREF pin voltage is not generated. When VDD is above 1 V and below the turnon threshold, the VREF pin is actively pulled low. This way, VREF can be used as a logic signal to indicate UVLO mode. If the bias voltage to VDD drops below the UVLO-OFF threshold, the PWM switching stops and VREF returns to 0 V. The device can be restarted by applying a voltage greater than the UVLO-ON threshold to the VDD pin.