6 Pin Configuration and Functions

Figure 6-1 D Package8-Pin SOICTop View

Table 6-1 Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
COMP	1	O	This pin provides the output of the error amplifier for compensation. In addition, the COMP pin is frequently used as a control port, by utilizing a secondary-side error amplifier to send an error signal across the secondary-primary isolation boundary through an opto-isolator. The error amplifier is internally current limited so the user can command zero duty cycle by externally forcing COMP to GND.
CS	3	I	Primary-side current sense pin. The current sense pin is the noninverting input to the PWM comparator. Connect to current sensing resistor. This signal is compared to a signal proportional to the error amplifier output voltage. The PWM uses this to terminate the OUT switch conduction. A voltage ramp can be applied to this pin to run the device with a voltage mode control configuration.
FB	2	I	This pin is the inverting input to the error amplifier. FB is used to control the power converter voltage-feedback loop for stability. The noninverting input to the error amplifier is internally trimmed to 2.5 V ±1%.
GND	5	—	Ground return pin for the output driver stage and the logic level controller section.
OUT	6	O	The output of the on-chip drive stage. OUT is intended to directly drive a MOSFET. The OUT pin in the UCC28C50-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C56H/L-Q1, and UCC28C58-Q1 is the same frequency as the oscillator, and can operate near 100% duty cycle. In the UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1, and UCC28C59-Q1, the frequency of OUT is one-half that of the oscillator due to an internal T flipflop. This limits the maximum duty cycle to < 50%. Peak currents of up to 1 A are sourced and sunk by this pin. OUT is actively held low when VDD is below the turn-on threshold.
RT/CT	4	I/O	Fixed frequency oscillator set point. Connect timing resistor (R_RT) to VREF and timing capacitor (C_CT) to GND from this pin to set the switching frequency. For best performance, keep the timing capacitor lead to the device GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions. The switching frequency (fSW) of the UCC28C50-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C56H/L and UCC28C58 gate drive is equal to fOSC; the switching frequency of the UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1, and UCC28C59-Q1 is equal to half of the f_OSC.
VDD	7	I	Analog controller bias input that provides power to the device. Total VDD current is the sum of the quiescent VDD current and the average OUT current. A bypass capacitor, typically 0.1 µF, connected directly to GND with minimal trace length, is required on this pin. Additional capacitance at least 10 times greater than the gate capacitance of the main switching FET used in the design and 10 times greater than the capacitance on the VREF pin are also required on VDD.
VREF	8	O	5-V reference voltage. VREF is used to provide charging current to the oscillator timing capacitor through the timing resistor. It is important for reference stability that VREF is bypassed to GND with a ceramic capacitor connected as close to the pin as possible. A minimum value of 0.1 µF ceramic is required. Additional VREF bypassing is required for external loads on VREF. No external voltage higher than specified VREF is allowed to superimposed to VREF pin Since VREF is an ouput.