10.1 Layout Guidelines

1. Decoupling capacitors should be placed as close to the device as possible.
2. BPCAP decoupling capacitors should be connected as close as possible to pin D6.
3. MARGIN pins output fast-edge PWM signals. These signals should be routed away from sensitive analog signals. It is a good practice to place R4 and C1 in Figure 16 as close as possible to the MARGIN pin, minimizing the propagation distance of the fast-edge PWM signals on the PCB. R3 can be placed near the power supply feedback node to isolate the feedback node from noise sources on the PCB. If R4 and C1 cannot be located close to the MARGIN pin, add a 20-Ω to 33-Ω series termination resistor located near the MARGIN pin.

10.2 Layout Example

UCD90240 is in a 157-pin BGA package. If UCD90240 is mounted on the top layer, decoupling capacitors can be placed on the bottom layer to make room for top-layer trace routing. The layout example below adopts such a strategy. Figure 35 shows bottom-layer component placement from top-view. In addition to Figure 35, note that:

1. A uniform ground plane should be used to connect DVSS, AVSS, and VREFA– pins.
2. All four BPCAP pins should be connected to a common internal-layer copper area.
3. AVSS and VREFA– pins can be connected to a common internal-layer copper area.

Figure 35. Bottom-layer Component Placement
(Top view, UCD90240 is Mounted on Top Layer)