The basic alarm for RBD overflow error is identified by read of alarms register. The mapping is as follows.

If 0x11C[4] = 1, JESD Lane 0/4 has RBD overflow error.

If 0x11D[4] = 1, JESD Lane 1/5 has RBD overflow error.

If 0x11E[4] = 1, JESD Lane 2/6 has RBD overflow error.

If 0x11F[4] = 1, JESD Lane 3/7 has RBD overflow error.

Depending on the page selected, the lane that has RBD overflow error can be identified. 0x16[2] provides information for lanes 0-3 and 0x16[3] for lanes 4-7.

Various possibilities in which RBD overflow alarm can happen is described as follows.

1. If the error shows up consistently across multiple configuration runs, it would mean that an invalid value of RBD is set. In this case, fcounter can be read back and optimal RBD can be set as described in Section 3 and Section 4.
2. If errors are intermittent, it could be either
   1. SYSREF not being latched deterministically across runs by AFE or FPGA/ASIC
   2. The FPGA/ASIC does not have a deterministic delay between SYSREF rising edge to start of EMB in 204C or start of ILA phase in 204B.
3. If running resync sequence (adcDacSync in CAFE) helps to solve the RBD error consistently, when it initially failed during the initial configuration run, it is possible that the SerDes did not adapt during the configuration sequence. Ensure that there exists data on the SRX lanes of AFE during the configuration.