This section describes the procedure to be followed for setting the optimal RBD. Figure 3-2⁽¹⁾ depicts the available features in AFE79xx to readout various latencies, including lane arrival delay and skew among lanes.

Internal to AFE79xx, there exists a LMFC counter which operates on a clock with frequency of LaneRate/40. The counter is periodic with the LMFC, whose frequency is LaneRate/(10*F*K). This means, the LMFC counter will count from 0 to F*K/4-1, as shown in Figure 3-2. There is also an option to add an offset to this counter by use of link0/1_init_o_counter. In Latte, this can be done by setting the system parameter jesdRxInitLmfcCounter. For example, as per Figure 3-2,

sysParams.jesdRxInitLmfcCounter = 5

can be added to the Latte bringup. See Section 5.3 for more details.

Lane arrival information can be read back from lane0/1/2/3_f_counter_any_lane_ready. lane0/1/2/3_f_counter_any_lane_ready is the value of LMFC counter when the transition from K28.5 to ILA occurs at the corresponding lane. Figure 3-2 shows such an example for JESD lane 0 and JESD lane 3. At JESD lane 0, ILA phase starts when the LMFC counter is 3, this information can be read back from lane0_f_counter_any_lane_ready. Similarly, lane3_f_counter_any_lane_ready would read as 6.

The instant last lane arrives is critical information for setting the RBD. This information can be read back from lane0/1/2/3_f_counter_all_lane_ready. lane0/1/2/3_f_counter_all_lane_ready would be equal to the lane_f_counter_any_lane_ready of slowest lane. In the case shown in Figure 3-2, the last lane to arrive is JESD lane 3. So, lane0/1/2/3_f_counter_all_lane_ready would read the same as lane3_f_counter_any_lane_ready, which is 6.

lane0/1/2/3_skew equals the difference between the LMFC counter values for earliest arrival lane and latest arrival lane. In Figure 3-2, it is difference between lane3_f_counter_any_lane_ready and lane0_f_counter_any_lane_ready. So lane0/1/2/3_skew would read 3.

With such visibility to lane arrival information in AFE79xx, it becomes easy to estimate the optimal RBD value. The recommended calculation for RBD is as follows:

The range of valid values the RBD can take is described by below condition:

and

Default value of buffer depth is 32. Buffer depth is configurable – value of (link0/1_buffer_depth + 1) determines the buffer depth. The register link0_buffer_depth can take values from 0 to 31, meaning buffer depth can vary from 1 to 32.

link0_rbd_m1 is written to with value of the RBD. Register map and procedure to be followed in system bringup is described in detail in Section 4. Below examples describe the basic RBD calculation.

From the latest arrival lane, a margin of 4 is accounted for to include temperature and process variations. Once the margin is added, modulus operation is performed with F*K/4. This is because the LMFC counter counts from 0 to a maximum of F*K/4-1. The buffer releases the aligned data on all lanes once the LMFC counter reaches the RBD value. In the example shown in Figure 3-2, the RBD is set to 10, which is 4 LMFC counter value ahead of latest arrival lane. Few more examples are shown below. The value of skew is assumed to be 3 in the examples.

Example 1

Example 2

Example 3