1 Introduction

The AFE79xx is a family of high-performance, wide bandwidth multi-channel transceivers, which includes four RF sampling transmitter chains. The transmitters support up to 1200-MHz wide bandwidth, which is designed for multi-band 4G and 5G base stations. Such high bandwidths demand up to 198 Gbps serial data transmission. For this reason, a maximum of 8 lanes are used to receive high bandwidth input for the DAC.

Each DAC takes a 16-bit I input and 16-bit Q input stream. For high bandwidth cases, the complex I and Q data reception can be spread among 4 input lanes. Figure 1-1 shows an example where the DAC JESD is configured with an LMFS⁽¹⁾ of 4222. Even with small form factor flip chip ball grid array (BGA) and symmetrical Serdes input and output ball placement, the PCB routing design cannot perfectly match all the SerDes I/O lanes. This causes a skew among lanes, which causes misalignment between the lanes. At the FPGA, data I0, I1, Q0 and Q1 are time aligned. As it traverses through the lanes and arrives at the AFE, the time alignment has been lost. If this is input to the DAC as it is, the spectrum observed at the DAC would be a lot different to what was expected. This example highlights the need to de-skew the receiver lanes in AFE. The role of RBD in JESD layer is exactly this.

Even in cases where a single lane carries data of each DAC, as in DAC JESD LMFS = 24410, it is critical to align the data on multiple lanes. Deterministic latency across power-up cycles necessitates this alignment across lanes. The path latency from FPGA to DAC is a critical metric and RBD helps with maintaining this deterministic latency across transmitter channels and across power-up cycles.