In this case, lanes in top JESD and bottom JESD are part of a single JESD link. In this case, based on lane0_f_counter_all_lane_ready in the first page, link0_rbd_m1 is set in the first page.

Example:

1. Read Page 0x16[2] : lane0_f_counter_all_lane_ready = 16

   getAllLaneReady(afeInst,0,&laneAllReady)

   laneAllReady = 16

2. Obtain valid range of RBD.

   getGoodRbdRange(afeInst,0,&rbdMin,&rbdMax)

   rbdMin = 17

   rbdMax = 35 (Based on skew = 3, rbdMax = min (allLaneReady) + BufferDepth -10 = 16 - 3 + 32 - 10).

3. In this example, optimal value is chosen as rbdMin + 3 = 20. In cases with multiple AFEs on a PCB, valid ranges can be looked at for all AFEs and optimal RBD can be chosen.
4. The optimal RBD is set and adcDacSync is run.

   setManualRbd(afeInst,0,20)

   adcDacSync(afeInst,1)

5. Read back link0_sysref_cnt_on_release_opportunity from the first page.

   getSysrefCntOnReleaseOpp(afeInst,0,&readVal)

   If readVal=1, optimal RBD is chosen as (20+1)%64 = 21

6. In the config, value of 21 is set for the link0_rbd_m1 in the first page. In Latte, sysParams.jesdRxRbd is set to [21,21,21,21]