SFFS088 April 2021 DRV8706-Q1
The failure mode distribution estimation for DRV8706-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
| Low side gate turned ON, when commanded OFF | 12.0% |
| Low side gate turned OFF, when commanded ON | 12.5% |
| Low side gate to source voltage too high or too low | 4.0% |
| Low side gate driver slew rate too fast or too slow | 3.0% |
| High side gate turned ON, when commanded OFF | 13.5% |
| High side gate turned OFF, when commanded ON | 16.0% |
| High side gate to source voltage too high or too low | 4.0% |
| High side gate driver slew rate too fast or too slow | 3.0% |
| Dead time between high side FET and low side FET transition incorrect | 5.5% |
| Current sense feedback and regulation incorrect | 10.0% |
| Drain Source voltage monitoring incorrect | 6.5% |
| Incorrect communication or fault indication | 10.0% |