SFFS127 March 2021 LM61480 , LM61495 , LM62460
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the LM62460, LM61480, and LM61495. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to Ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the LM62460, LM61480, and LM61495 pin diagram. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the LM62460, LM61480, and LM61495 datasheet.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Application circuit, as per the LM61495-Q1 data sheet is used.
| Pin Name | Pin No | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| PGND2 | 1 | Normal Operation | D |
| VIN2 | 2 | VOUT = 0 V | B |
| RBOOT | 3 | VOUT = 0 V, damage if VIN > 5.5 V | A |
| CBOOT | 4 | VOUT = 0 V | B |
| BIAS | 5 | Normal Operation | D |
| VCC | 6 | VOUT = 0 V | B |
| FB | 7 | VOUT >> than programmed output voltage | B |
| AGND | 8 | Normal Operation | D |
| RT | 9 | Switch frequency = 2.2 MHz | C |
| RESET | 10 | RESET value not valid. VOUT normal | D |
| SPSP | 11 | Spread spectrum off | C |
| SYNC/MODE | 12 | Mode = Auto PFM at light load. VOUT normal | C |
| EN | 13 | VOUT = 0 V | B |
| VIN1 | 14 | VOUT = 0 V | B |
| PGND1 | 15 | Normal Operation | D |
| SW | 16 | Damage to HS FET | A |
| Pin Name | Pin No | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| PGND2 | 1 | VOUT normal. Current loop will be affected, potentially affecting noise/jitter/EMI/reliability. | C |
| VIN2 | 2 | VOUT normal. All current will be in other VIN1 loop, potentially affecting noise/jitter/EMI/reliability | C |
| RBOOT | 3 | VOUT normal, lower efficiency, higher junction temp | C |
| CBOOT | 4 | VOUT = 0 V | B |
| BIAS | 5 | Normal Operation | D |
| VCC | 6 | VCC output can oscillate and internal circuitry may not function correctly | B |
| FB | 7 | VOUT >> than programmed output voltage | B |
| AGND | 8 | VOUT might be abnormal due to switching noise on analog circuits | B |
| RT | 9 | Switch frequency may become unstable | B |
| RESET | 10 | RESET signal not valid. Normal operation | C |
| SPSP | 11 | Spread spectrum enable/disable can be unstable | C |
| SYNC/MODE | 12 | Mode may switch randomly. Unpredictable behavior | C |
| EN | 13 | Device can shut off | B |
| VIN1 | 14 | VOUT normal. All current will be in other VIN2 loop, potentially affecting noise/jitter/EMI/reliability | C |
| PGND1 | 15 | VOUT normal. Current loop will be affected, potentially affecting noise/jitter/EMI/reliability. | C |
| SW | 16 | VOUT = 0 V | B |
| Pin Name | Pin No | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| PGND2 | 1 | VOUT =0 V. Damage to low-side circuitry if PGND >> AGND | B |
| VIN2 | 2 | VOUT = 0 V | B |
| RBOOT | 3 | VOUT normal | D |
| CBOOT | 4 | VOUT = 0 V | B |
| BIAS | 5 | VCC ESD clamp damaged if BIAS > 5 V | A |
| VCC | 6 | VOUT = 0 V | C |
| FB | 7 | VOUT >> than programmed output voltage | B |
| AGND | 8 | Switch frequency = 2.2 MHz | C |
| RT | 9 | Switch frequency may change, RT can become damaged if RESET > 5.5 V. RESET may not be valid | B |
| RESET | 10 | Spread spectrum can enable/disable, RESET can become damaged if biased above 20 V. | A |
| SPSP | 11 | Spread spectrum, sync, and mode functionality can be unstable. | C |
| SYNC/MODE | 12 | Can disable device, change modes, or interrupt syncing | B |
| EN | 13 | Device enabled | B |
| VIN1 | 14 | VOUT = 0 V. Damage to low-side circuitry if PGND >> AGND | B |
| PGND1 | 15 | VOUT = 0 V. Damage to low-side circuitry if PGND >> AGND | B |
| SW | 16 | Damage to HS FET | A |
| Pin Name | Pin No | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| PGND2 | 1 | VOUT = 0 V. Damage to low-side circuitry if PGND >> AGND | B |
| VIN2 | 2 | Normal operation | D |
| RBOOT | 3 | VOUT = 0 V. RBOOT ESD clamp will run current to destruction. | A |
| CBOOT | 4 | VOUT = 0 V. CBOOT ESD clamp will run current to destruction. | A |
| BIAS | 5 | If VIN exceeds 16 V damage will occur. If below, normal operation | A |
| VCC | 6 | If VIN exceeds 5.5 V damage will occur. | A |
| FB | 7 | If VIN exceeds 16 V (fixed version) or 5.5 V (adjustable version) damage will occur. VOUT = 0 V | A |
| AGND | 8 | VOUT = 0 V. Damage to other pins referred to GND. | A |
| RT | 9 | If VIN exceeds 5.5 V damage will occur. VOUT = 0 V | A |
| RESET | 10 | If VIN exceeds 20 V damage will occur. VOUT = 0 V | A |
| SPSP | 11 | Spread spectrum enabled | D |
| SYNC/MODE | 12 | Mode set to FPWM | C |
| EN | 13 | Device enabled | C |
| VIN1 | 14 | Normal operation | D |
| PGND1 | 15 | VOUT = 0 V. Damage to low-side circuitry if PGND >> AGND | B |
| SW | 16 | Damage to LS FET | A |