SFFS533 October 2022 LM51231-Q1
This section provides a failure mode analysis (FMA) for the pins of the LM51231-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Figure 4-1 shows the LM51231-Q1 pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the LM51231-Q1 data sheet.
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| CSP | 1 | CSP Pin can be damaged due to the differential voltage exceeds the 0.3V abs max rating. | A |
| CSN | 2 | CSN Pin can be damaged due to the differential voltage exceeds the 0.3V abs max rating. | A |
| VOUT/SENSE | 3 | VOUT out of regulation, possible over charge of the output voltage | A |
| PGOOD | 4 | Correct output voltage, but loss of power-good functionality. | C |
| HO | 5 | High-side driver can be damaged when SW voltage rises | A |
| SW | 6 | No energy transferred from input to output | B |
| HB | 7 | Can be damaged when SW voltage rises | A |
| BIAS | 8 | Device unpowered and therefore not functional. | B |
| VCC | 9 | Loss of VCC regulation, no switching | B |
| PGND | 10 | No effect. | D |
| LO | 11 | VOUT out of regulation. LO stops switching. | B |
| MODE | 12 | Diode emulation mode is activated. No effect in case the device is configured for diode emulation mode (MODE = GND). | C |
| UVLO/EN | 13 | Device is disabled. | B |
| SYNC/DITHER/VH | 14 | External Clock Synchronization is disabled. Spread Spectrum is disabled. VCC is not hold when EN = GND. No effect in case External Clock Synchronization and Spread Spectrum are disabled as well as the VCC hold function is disabled (SYNC/DITHER/VH = GND). | C |
| RT | 15 | Maximum switching frequency much greater than 2.21 MHz | C |
| VREF/RANGE | 16 | No switching. Target output voltage is 0 V | B |
| SS | 17 | Device does not start, no switching | B |
| TRK | 18 | VOUT out of regulation, no switching | B |
| AGND | 19 | No effect. | D |
| COMP | 20 | VOUT out of regulation, not switching. | B |
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| CSP | 1 | Loss of current sense signal. | B |
| CSN | 2 | Loss of current sense signal. | B |
| VOUT/SENSE | 3 | VOUT out of regulation, possible over charge of the output voltage | A |
| PGOOD | 4 | Correct output voltage, but loss of power-good functionality. | C |
| HO | 5 | Loss of high side driver. Operating with sync FET body diode conducting. | C |
| SW | 6 | Loss of high side driver. Operating with sync FET body diode conducting. | C |
| HB | 7 | Loss of boot voltage and hence high side driver. Operating with sync FET body diode conducting. | C |
| BIAS | 8 | Device unpowered and therefore not functional. | B |
| VCC | 9 | No stable VCC to sustain normal operation | B |
| PGND | 10 | Possible device damage. | A |
| LO | 11 | Low-side MOSFET never switched. | B |
| MODE | 12 | No effect if diode emulation mode is active, otherwise diode emulation mode is activated. | C |
| UVLO/EN | 13 | Device is disabled. | B |
| SYNC/DITHER/VH | 14 | Loss of VCC hold up functionality | C |
| RT | 15 | Minimum frequency is set. | C |
| VREF/RANGE | 16 | VOUT out of regulation, | B |
| SS | 17 | Small soft-start time. Normal operation after | C |
| TRK | 18 | VOUT out of regulation | B |
| AGND | 19 | Possible device damage. | A |
| COMP | 20 | Device may be unstable. | C |
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class | ||||
|---|---|---|---|---|---|---|---|---|
| CSP | 1 | CSN | Loss of current sense information. Circuit possibly unstable | C | ||||
| CSN | 2 | VOUT/SENSE | Possible damage. Exceeds absolute maximum voltage rating | A | ||||
| VOUT/SENSE | 3 | PGOOD | Loss of VOUT feedback. Possibly unstable operation | B | ||||
| PGOOD | 4 | HO | No damage, loss of PGOOD function | B | ||||
| HO | 5 | SW | Loss of high side driver. Operating with sync FET body diode conducting. | B | ||||
| SW | 6 | HB | Loss of boot voltage and hence high side driver. Operating with sync FET body diode conducting. | B | ||||
| HB | 7 | BIAS | Possible damage. HB exceeds absolute maximum voltage rating | A | ||||
| BIAS | 8 | VCC | Possible damage to VCC if BIAS is above the absolute maximum voltage rating of VCC, otherwise no damage | A | ||||
| VCC | 9 | PGND | No VCC rail, no switching | B | ||||
| PGND | 10 | LO | LO never turns on. Switching never happens | B | ||||
| LO | 11 | MODE | Switching mode toggles with every switching cycle | C | ||||
| MODE | 12 | UVLO/EN | Switching mode set by the UVLO/EN pin voltage | B | ||||
| UVLO/EN | 13 | SYNC/DITHER/VH | SYNC/DITHER/VH setting set by the UVLO/EN pin | B | ||||
| SYNC/DITHER/VH | 14 | RT | Can exceed the RT absolute maximum voltage | A | ||||
| RT | 15 | VREF/RANGE | Switching frequency will not be correct | C | ||||
| VREF/RANGE | 16 | SS | Small soft-start time | C | ||||
| SS | 17 | TRK | TRK > 1.2V will stop any switching on the controller. | B | ||||
| TRK | 18 | AGND | VOUT out of regulation, no switching | B | ||||
| AGND | 19 | COMP | VOUT out of regulation, not switching. | B | ||||
| COMP | 20 | CSP | Possible damage. Exceeds absolute maximum voltage rating of COMP | A | ||||
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| CSP | 1 | Normal operation | D |
| CSN | 2 | Loss of current sense signal. Circuit possibly unstable | C |
| VOUT/SENSE | 3 | VOUT out of regulation | B |
| PGOOD | 4 | Loss of PGOOD functionality | C |
| HO | 5 | HO pin can exceed the HO to SW absolute maximum voltage rating | A |
| SW | 6 | No energy is transferred from input to output | B |
| HB | 7 | HB exceeds HB to SW absolute maximum voltage rating | A |
| BIAS | 8 | Normal operation | D |
| VCC | 9 | VCC exceeds absolute maximum voltage rating | A |
| PGND | 10 | Possible damage | A |
| LO | 11 | Possible damage. Exceeds absolute maximum voltage rating | A |
| MODE | 12 | Possible damage. Exceeds absolute maximum voltage rating | A |
| UVLO/EN | 13 | No UVLO functionality | C |
| SYNC/DITHER/VH | 14 | Possible damage. Exceeds absolute maximum voltage rating | A |
| RT | 15 | Possible damage. Exceeds absolute maximum voltage rating | A |
| VREF/RANGE | 16 | Possible damage. Exceeds absolute maximum voltage rating | A |
| SS | 17 | Possible damage. Exceeds absolute maximum voltage rating | A |
| TRK | 18 | Possible damage. Exceeds absolute maximum voltage rating | A |
| AGND | 19 | Possible damage. Exceeds absolute maximum voltage rating | A |
| COMP | 20 | Possible damage. Exceeds absolute maximum voltage rating | A |