SLAS590P March 2009 – September 2020
PRODUCTION DATA
- 1 Features
- 2 Applications
- 3 Description
- 4 Functional Block Diagrams
- 5 Revision History
- 6 Device Comparison
- 7 Terminal Configuration and Functions
-
8 Specifications
- 8.1 Absolute Maximum Ratings
- 8.2 ESD Ratings
- 8.3 Recommended Operating Conditions
- 8.4 Active Mode Supply Current Into VCC Excluding External Current
- 8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
- 8.6 Thermal Resistance Characteristics
- 8.7 Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
- 8.8 Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
- 8.9 Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
- 8.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
- 8.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
- 8.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
- 8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
- 8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
- 8.15 Crystal Oscillator, XT1, Low-Frequency Mode
- 8.16 Crystal Oscillator, XT2
- 8.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- 8.18 Internal Reference, Low-Frequency Oscillator (REFO)
- 8.19 DCO Frequency
- 8.20 PMM, Brownout Reset (BOR)
- 8.21 PMM, Core Voltage
- 8.22 PMM, SVS High Side
- 8.23 PMM, SVM High Side
- 8.24 PMM, SVS Low Side
- 8.25 PMM, SVM Low Side
- 8.26 Wake-up Times From Low-Power Modes and Reset
- 8.27 Timer_A
- 8.28 Timer_B
- 8.29 USCI (UART Mode) Clock Frequency
- 8.30 USCI (UART Mode)
- 8.31 USCI (SPI Master Mode) Clock Frequency
- 8.32 USCI (SPI Master Mode)
- 8.33 USCI (SPI Slave Mode)
- 8.34 USCI (I2C Mode)
- 8.35 12-Bit ADC, Power Supply and Input Range Conditions
- 8.36 12-Bit ADC, Timing Parameters
- 8.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
- 8.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
- 8.39 12-Bit ADC, Temperature Sensor and Built-In VMID
- 8.40 REF, External Reference
- 8.41 REF, Built-In Reference
- 8.42 Comparator_B
- 8.43 Ports PU.0 and PU.1
- 8.44 USB Output Ports DP and DM
- 8.45 USB Input Ports DP and DM
- 8.46 USB-PWR (USB Power System)
- 8.47 USB-PLL (USB Phase-Locked Loop)
- 8.48 Flash Memory
- 8.49 JTAG and Spy-Bi-Wire Interface
-
9 Detailed Description
- 9.1 CPU
- 9.2 Operating Modes
- 9.3 Interrupt Vector Addresses
- 9.4 Memory Organization
- 9.5 Bootloader (BSL)
- 9.6 JTAG Operation
- 9.7 Flash Memory
- 9.8 RAM
- 9.9
Peripherals
- 9.9.1 Digital I/O
- 9.9.2 Port Mapping Controller
- 9.9.3 Oscillator and System Clock
- 9.9.4 Power-Management Module (PMM)
- 9.9.5 Hardware Multiplier
- 9.9.6 Real-Time Clock (RTC_A)
- 9.9.7 Watchdog Timer (WDT_A)
- 9.9.8 System Module (SYS)
- 9.9.9 DMA Controller
- 9.9.10 Universal Serial Communication Interface (USCI)
- 9.9.11 TA0
- 9.9.12 TA1
- 9.9.13 TA2
- 9.9.14 TB0
- 9.9.15 Comparator_B
- 9.9.16 ADC12_A
- 9.9.17 CRC16
- 9.9.18 Voltage Reference (REF) Module
- 9.9.19 Universal Serial Bus (USB)
- 9.9.20 Embedded Emulation Module (EEM)
- 9.9.21 Peripheral File Map
- 9.10
Input/Output Diagrams
- 9.10.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
- 9.10.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
- 9.10.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
- 9.10.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
- 9.10.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
- 9.10.6 Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
- 9.10.7 Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
- 9.10.8 Port P5 (P5.6 and P5.7) Input/Output With Schmitt Trigger
- 9.10.9 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
- 9.10.10 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
- 9.10.11 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
- 9.10.12 Port P8 (P8.0 to P8.2) Input/Output With Schmitt Trigger
- 9.10.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports
- 9.10.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
- 9.10.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
- 9.11 Device Descriptors (TLV)
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
9.1 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers (see Figure 9-1).
Peripherals are connected to the CPU using data, address, and control buses. The peripherals can be managed with all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Figure 9-1 Integrated CPU Registers