SLASEB7D June 2017 – December 2020
PRODUCTION DATA
- 1 Features
- 2 Applications
- 3 Description
- 4 Functional Block Diagrams
- 5 Revision History
- 6 Device Comparison
- 7 Terminal Configuration and Functions
-
8 Specifications
- 8.1 Absolute Maximum Ratings
- 8.2 ESD Ratings
- 8.3 Recommended Operating Conditions
- 8.4 Active Mode Supply Current Into VCC Excluding External Current
- 8.5 Typical Characteristics, Active Mode Supply Currents
- 8.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
- 8.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
- 8.8 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
- 8.9 Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
- 8.10 Typical Characteristics, Low-Power Mode Supply Currents
- 8.11 Typical Characteristics, Current Consumption per Module (1)
- 8.12 Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
- 8.13
Timing and Switching Characteristics
- 8.13.1 Power Supply Sequencing
- 8.13.2 Reset Timing
- 8.13.3 Clock Specifications
- 8.13.4 Wake-up Characteristics
- 8.13.5 Digital I/Os
- 8.13.6 LEA
- 8.13.7 Timer_A and Timer_B
- 8.13.8
eUSCI
- 8.13.8.1 eUSCI (UART Mode) Clock Frequency
- 8.13.8.2 eUSCI (UART Mode) Switching Characteristics
- 8.13.8.3 eUSCI (SPI Master Mode) Clock Frequency
- 8.13.8.4 eUSCI (SPI Master Mode) Switching Characteristics
- 8.13.8.5 eUSCI (SPI Master Mode) Timing Diagrams
- 8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics
- 8.13.8.7 eUSCI (SPI Slave Mode) Timing Diagrams
- 8.13.8.8 eUSCI (I2C Mode) Switching Characteristics
- 8.13.8.9 eUSCI (SPI Slave Mode) Timing Diagrams
- 8.13.9 Segment LCD Controller
- 8.13.10
ADC12_B
- 8.13.10.1 12-Bit ADC, Power Supply and Input Range Conditions
- 8.13.10.2 12-Bit ADC, Timing Parameters
- 8.13.10.3 12-Bit ADC, Linearity Parameters
- 8.13.10.4 12-Bit ADC, Dynamic Performance With External Reference
- 8.13.10.5 12-Bit ADC, Dynamic Performance With Internal Reference
- 8.13.10.6 12-Bit ADC, Temperature Sensor and Built-In V1/2
- 8.13.10.7 12-Bit ADC, External Reference
- 8.13.10.8 Temperature Sensor Typical Characteristics
- 8.13.11 Reference
- 8.13.12 Comparator
- 8.13.13 FRAM
- 8.13.14 USS
- 8.13.15 Emulation and Debug
-
9 Detailed Description
- 9.1 Overview
- 9.2 CPU
- 9.3 Ultrasonic Sensing Solution (USS) Module
- 9.4 Low-Energy Accelerator (LEA) for Signal Processing
- 9.5 Operating Modes
- 9.6 Interrupt Vector Table and Signatures
- 9.7 Bootloader (BSL)
- 9.8 JTAG Operation
- 9.9 FRAM Controller A (FRCTL_A)
- 9.10 RAM
- 9.11 Tiny RAM
- 9.12 Memory Protection Unit (MPU) Including IP Encapsulation
- 9.13
Peripherals
- 9.13.1 Digital I/O
- 9.13.2 Oscillator and Clock System (CS)
- 9.13.3 Power-Management Module (PMM)
- 9.13.4 Hardware Multiplier (MPY)
- 9.13.5 Real-Time Clock (RTC_C)
- 9.13.6 Measurement Test Interface (MTIF)
- 9.13.7 Watchdog Timer (WDT_A)
- 9.13.8 System Module (SYS)
- 9.13.9 DMA Controller
- 9.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
- 9.13.11 TA0, TA1, and TA4
- 9.13.12 TA2 and TA3
- 9.13.13 TB0
- 9.13.14 ADC12_B
- 9.13.15 USS
- 9.13.16 Comparator_E
- 9.13.17 CRC16
- 9.13.18 CRC32
- 9.13.19 AES256 Accelerator
- 9.13.20 True Random Seed
- 9.13.21 Shared Reference (REF)
- 9.13.22 LCD_C
- 9.13.23 Embedded Emulation
- 9.14
Input/Output Diagrams
- 9.14.1 Port Function Select Registers (PySEL1 , PySEL0)
- 9.14.2 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
- 9.14.3 Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
- 9.14.4 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
- 9.14.5 Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
- 9.14.6 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
- 9.14.7 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
- 9.14.8 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
- 9.14.9 Port P6 (P6.0) Input/Output With Schmitt Trigger
- 9.14.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
- 9.14.11 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
- 9.14.12 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
- 9.14.13 Port P7 (P7.4) Input/Output With Schmitt Trigger
- 9.14.14 Port P7 (P7.5) Input/Output With Schmitt Trigger
- 9.14.15 Port P7 (P7.6 and P7.7) Input/Output With Schmitt Trigger
- 9.14.16 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
- 9.14.17 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
- 9.14.18 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
- 9.14.19 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
- 9.14.20 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
- 9.14.21 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
- 9.15 Device Descriptors (TLV)
- 9.16 Memory Map
- 9.17 Identification
-
10Applications, Implementation, and Layout
- 10.1
Device Connection and Layout Fundamentals
- 10.1.1 Power Supply Decoupling and Bulk Capacitors
- 10.1.2 External Oscillator (HFXT and LFXT)
- 10.1.3 USS Oscillator (USSXT)
- 10.1.4 Transducer Connection to the USS Module
- 10.1.5 Charge Pump Control of Input Multiplexer
- 10.1.6 JTAG
- 10.1.7 Reset
- 10.1.8 Unused Pins
- 10.1.9 General Layout Recommendations
- 10.1.10 Do's and Don'ts
- 10.2 Peripheral- and Interface-Specific Design Information
- 10.1
Device Connection and Layout Fundamentals
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
9.14.19 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
Figure 9-20 shows the port diagram. Table 9-42 summarizes the selection of the pin function.
Functional representation only.
Figure 9-20 Port PJ (PJ.0 to PJ.3) DiagramTable 9-42 Port PJ (PJ.0 to PJ.3) Pin Functions
| PIN NAME (PJ.x) | x | FUNCTION | CONTROL BITS/ SIGNALS(1) | |||
|---|---|---|---|---|---|---|
| PJDIR.x | PJSEL1.x | PJSEL0.x | CEPDx (Cx) | |||
| PJ.0/TDO/ACLK/SRSCG1/DMAE0/C10 | 0 | PJ.0 (I/O)(2) | 0 = Input, 1 = Output | 0 | 0 | 0 |
| TDO(3) | X | X | X | 0 | ||
| N/A | 0 | 0 | 1 | 0 | ||
| ACLK | 1 | |||||
| N/A | 0 | 1 | 0 | 0 | ||
| CPU Status Register Bit SCG1 | 1 | |||||
| DMAE0 | 0 | 1 | 1 | 0 | ||
| Internally tied to DVSS | 1 | |||||
| C10(5) | X | X | X | 1 | ||
| PJ.1/TDI/TCLK/SMCLK/SRSCG0/TA4CLK/C11 | 1 | PJ.1 (I/O)(2) | 0 = Input, 1 = Output | 0 | 0 | 0 |
| TDI/TCLK(3) (4) | X | X | X | 0 | ||
| N/A | 0 | 0 | 1 | 0 | ||
| SMCLK | 1 | |||||
| N/A | 0 | 1 | 0 | 0 | ||
| CPU Status Register Bit SCG0 | 1 | |||||
| TA4CLK | 0 | 1 | 1 | 0 | ||
| Internally tied to DVSS | 1 | |||||
| C11(5) | X | X | X | 1 | ||
| PJ.2/TMS/MCLK/SROSCOFF/TB0OUTH/C12 | 2 | PJ.2 (I/O)(2) | I: 0; O: 1 | 0 | 0 | 0 |
| TMS(3) (4) | X | X | X | 0 | ||
| N/A | 0 | 0 | 1 | 0 | ||
| MCLK | 1 | |||||
| N/A | 0 | 1 | 0 | 0 | ||
| CPU Status Register Bit OSCOFF | 1 | |||||
| TB0OUTH | 0 | 1 | 1 | 0 | ||
| Internally tied to DVSS | 1 | |||||
| C12(5) | X | X | X | 1 | ||
| PJ.3/TCK/RTCCLK/SRCPUOFF/TB0.6/C13 | 3 | PJ.3 (I/O)(2) | I: 0; O: 1 | 0 | 0 | 0 |
| TCK(3) (4) | X | X | X | 0 | ||
| N/A | 0 | 0 | 1 | 0 | ||
| RTCCLK | 1 | |||||
| N/A | 0 | 1 | 0 | 0 | ||
| CPU Status Register Bit CPUOFF | 1 | |||||
| TB0.CCI6A | 0 | 1 | 1 | 0 | ||
| TB0.6 | 1 | |||||
| C13(5) | X | X | X | 1 | ||
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made through the SYS module or by the Spy-Bi-Wire four-wire entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPDx bits have an effect in these cases.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
(5) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables The output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.