米6体育平台手机版

SLASEB7D June 2017 – December 2020

PRODUCTION DATA

7.2 Pin Attributes

Table 7-1 lists the attributes of each pin.

Table 7-1 Pin Attributes

PIN NUMBER	SIGNAL NAME⁽¹⁾⁽⁴⁾	SIGNAL TYPE⁽²⁾	BUFFER TYPE⁽³⁾	POWER SOURCE⁽⁵⁾	RESET STATE AFTER BOR⁽⁷⁾
1	P2.2	I/O	LVCMOS	DVCC	OFF
	COUT	O	LVCMOS	DVCC	–
	UCA0CLK	I/O	LVCMOS	DVCC	–
	A14	I	Analog	DVCC	–
	C14	I	Analog	DVCC	–
2	P2.3	I/O	LVCMOS	DVCC	OFF
	TA0.0	I/O	LVCMOS	DVCC	–
	UCA0STE	I/O	LVCMOS	DVCC	–
	A15	I	Analog	DVCC	–
	C15	I	Analog	DVCC	–
3	P1.0	I/O	LVCMOS	DVCC	OFF
	UCA1CLK	I/O	LVCMOS	DVCC	–
	TA1.0	I/O	LVCMOS	DVCC	–
	A0	I	Analog	DVCC	–
	C0	I	Analog	DVCC	–
	VREF-	O	Analog	DVCC	–
	VeREF-	I	Analog	DVCC	–
4	P1.1	I/O	LVCMOS	DVCC	OFF
	UCA1STE	I/O	LVCMOS	DVCC	–
	TA4.0	I/O	LVCMOS	DVCC	–
	A1	I	Analog	DVCC	–
	C1	I	Analog	DVCC	–
	VREF+	O	Analog	DVCC	–
	VeREF+	I	Analog	DVCC	–
5	AVSS2	P	Power	–	N/A
6	PJ.4	I/O	LVCMOS	DVCC	OFF
6	LFXIN	I	Analog	DVCC	–
7	PJ.5	I/O	LVCMOS	DVCC	OFF
7	LFXOUT	O	Analog	DVCC	–
8	AVSS3	P	Power	–	N/A
9	PJ.6	I/O	LVCMOS	DVCC	–
9	HFXIN	I	Analog	DVCC	–
10	PJ.7	I/O	LVCMOS	DVCC	OFF
10	HFXOUT	O	Analog	DVCC	–
11	AVSS4	P	Power	–	N/A
12	P1.4	I/O	LVCMOS	DVCC	OFF
	TB0.4	I/O	LVCMOS	DVCC	–
	UCB0STE	I/O	LVCMOS	DVCC	–
	A2	I	Analog	DVCC	–
	C2	I	Analog	DVCC	–
13	P1.5	I/O	LVCMOS	DVCC	OFF
	TB0.5	I/O	LVCMOS	DVCC	–
	UCB0CLK	I/O	LVCMOS	DVCC	–
	A3	I	Analog	DVCC	–
	C3	I	Analog	DVCC	–
14	P1.6	I/O	LVCMOS	DVCC	OFF
	UCB0SIMO	I/O	LVCMOS	DVCC	–
	UCB0SDA	I/O	LVCMOS	DVCC	–
	A4	I	Analog	DVCC	–
	C4	I	Analog	DVCC	–
15	P1.7	I/O	LVCMOS	DVCC	OFF
	USSTRG	I	LVCMOS	DVCC	–
	UCB0SOMI	I/O	LVCMOS	DVCC	–
	UCB0SCL	I/O	LVCMOS	DVCC	–
	A5	I	Analog	DVCC	–
	C5	I	Analog	DVCC	–
16	P2.0	I/O	LVCMOS	DVCC	OFF
	UCA0TXD	O	LVCMOS	DVCC	–
	UCA0SIMO	I/O	LVCMOS	DVCC	–
	A6	I	Analog	DVCC	–
	C6	I	Analog	DVCC	–
17	P2.1	I/O	LVCMOS	DVCC	OFF
	UCA0RXD	I	LVCMOS	DVCC	–
	UCA0SOMI	I/O	LVCMOS	DVCC	–
	A7	I	Analog	DVCC	–
	C7	I	Analog	DVCC	–
18	P1.2	I/O	LVCMOS	DVCC	OFF
	UCA1TXD	O	LVCMOS	DVCC	–
	UCA1SIMO	I/O	LVCMOS	DVCC	–
	A8	I	Analog	DVCC	–
	C8	I	Analog	DVCC	–
19	P1.3	I/O	LVCMOS	DVCC	OFF
	UCA1RXD	I	LVCMOS	DVCC	–
	UCA1SOMI	I/O	LVCMOS	DVCC	–
	A9	I	Analog	DVCC	–
	C9	I	Analog	DVCC	–
20	TEST	I	LVCMOS	DVCC	PD
20	SBWTCK	I	LVCMOS	DVCC	–
21	RST	I/O	LVCMOS	DVCC	PU
	NMI	I	LVCMOS	DVCC	–
	SBWTDIO	I/O	LVCMOS	DVCC	–
22	PJ.0	I/O	LVCMOS	DVCC	OFF
	TDO	O	LVCMOS	DVCC	–
	ACLK	O	LVCMOS	DVCC	–
	SRSCG1	O	LVCMOS	DVCC	–
	DMAE0	I	LVCMOS	DVCC	–
	C10	I	Analog	DVCC	–
23	PJ.1	I/O	LVCMOS	DVCC	OFF
	TDI	I	LVCMOS	DVCC	–
	TCLK	I	LVCMOS	DVCC	–
	SMCLK	O	LVCMOS	DVCC	–
	SRSCG0	O	LVCMOS	DVCC	–
	TA4CLK	I	LVCMOS	DVCC	–
	C11	I	Analog	DVCC	–
24	PJ.2	I/O	LVCMOS	DVCC	OFF
	TMS	I	LVCMOS	DVCC	–
	MCLK	O	LVCMOS	DVCC	–
	SROSCOFF	O	LVCMOS	DVCC	–
	TB0OUTH	I	LVCMOS	DVCC	–
	C12	I	Analog	DVCC	–
25	PJ.3	I/O	LVCMOS	DVCC	OFF
	TCK	I	LVCMOS	DVCC	–
	RTCCLK	O	LVCMOS	DVCC	–
	SRCPUOFF	O	LVCMOS	DVCC	–
	TB0.6	I/O	LVCMOS	DVCC	–
	C13	I	Analog	DVCC	–
26	DVSS1	P	Power	–	N/A
27	DVCC1	P	Power	–	N/A
28	P2.4	I/O	LVCMOS	DVCC	OFF
	TA0CLK	I	LVCMOS	DVCC	–
	TB0CLK	I	LVCMOS	DVCC	–
	TA1CLK	I	LVCMOS	DVCC	–
	S32	O	Analog	DVCC	–
29	P2.5	I/O	LVCMOS	DVCC	OFF
	TA4.0	I/O	LVCMOS	DVCC	–
	S31	O	Analog	DVCC	–
30	P2.6	I/O	LVCMOS	DVCC	OFF
	TA4.1	I/O	LVCMOS	DVCC	–
	S30	O	Analog	DVCC	–
31	P3.0	I/O	LVCMOS	DVCC	OFF
	TB0.0	I/O	LVCMOS	DVCC	–
	S29	O	Analog	DVCC	–
32	P3.1	I/O	LVCMOS	DVCC	OFF
	TB0.1	O	LVCMOS	DVCC	–
	S28	O	Analog	DVCC	–
33	P3.2	I/O	LVCMOS	DVCC	OFF
	TB0.2	O	LVCMOS	DVCC	–
	S27	O	Analog	DVCC	–
34	P3.3	I/O	LVCMOS	DVCC	OFF
	TB0.3	I/O	LVCMOS	DVCC	–
	S26	O	Analog	DVCC	–
35	P3.4	I/O	LVCMOS	DVCC	OFF
	TB0OUTH	I	LVCMOS	DVCC	–
	S25	O	Analog	DVCC	–
36	P3.5	I/O	LVCMOS	DVCC	OFF
	TB0.4	I/O	LVCMOS	DVCC	–
	S24	O	Analog	DVCC	–
37	P3.6	I/O	LVCMOS	DVCC	OFF
	TB0.5	I/O	LVCMOS	DVCC	–
	S23	O	Analog	DVCC	–
38	P3.7	I/O	LVCMOS	DVCC	OFF
	TB0.6	I/O	LVCMOS	DVCC	–
	S22	O	Analog	DVCC	–
39	P2.7	I/O	LVCMOS	DVCC	OFF
	TA0.0	I/O	LVCMOS	DVCC	–
	S21	O	Analog	DVCC	–
40	P9.0	I/O	LVCMOS	DVCC	OFF
	TA1.0	I/O	LVCMOS	DVCC	–
	S20	O	Analog	DVCC	–
41	P9.1	I/O	LVCMOS	DVCC	OFF
	SMCLK	O	LVCMOS	DVCC	–
	S19	O	Analog	DVCC	–
42	P9.2	I/O	LVCMOS	DVCC	OFF
	MCLK	O	LVCMOS	DVCC	–
	S18	O	Analog	DVCC	–
43	P9.3	I/O	LVCMOS	DVCC	OFF
	ACLK	O	LVCMOS	DVCC	–
	S17	O	Analog	DVCC	–
44	P4.0	I/O	LVCMOS	DVCC	OFF
	RTCCLK	O	LVCMOS	DVCC	–
	S16	O	Analog	DVCC	–
45	P4.1	I/O	LVCMOS	DVCC	OFF
	UCA0CLK	I/O	LVCMOS	DVCC	–
	S15	O	Analog	DVCC	–
46	P4.2	I/O	LVCMOS	DVCC	OFF
	UCA0STE	I/O	LVCMOS	DVCC	–
	S14	O	Analog	DVCC	–
47	P4.3	I/O	LVCMOS	DVCC	OFF
	UCA0TXD	O	LVCMOS	DVCC	–
	UCA0SIMO	I/O	LVCMOS	DVCC	–
	S13	O	Analog	DVCC	–
48	P4.4	I/O	LVCMOS	DVCC	OFF
	UCA0RXD	I	LVCMOS	DVCC	–
	UCA0SOMI	I/O	LVCMOS	DVCC	–
	S12	O	Analog	DVCC	–
49	P4.5	I/O	LVCMOS	DVCC	OFF
	TA0CLK	I	LVCMOS	DVCC	–
	TA1CLK	I	LVCMOS	DVCC	–
	S11	O	Analog	DVCC	–
50	P4.6	I/O	LVCMOS	DVCC	OFF
	TB0CLK	I	LVCMOS	DVCC	–
	TA4CLK	I	LVCMOS	DVCC	–
	S10	O	Analog	DVCC	–
51	DVSS2	P	Power	–	N/A
52	DVCC2	P	Power	–	N/A
53	P4.7	I/O	LVCMOS	DVCC	OFF
	DMAE0	I	LVCMOS	DVCC	–
	S9	O	Analog	DVCC	–
54	P5.0	I/O	LVCMOS	DVCC	OFF
	UCA2TXD	O	LVCMOS	DVCC	–
	UCA2SIMO	I/O	LVCMOS	DVCC	–
	S8	O	Analog	DVCC	–
55	P5.1	I/O	LVCMOS	DVCC	OFF
	UCA2RXD	I	LVCMOS	DVCC	–
	UCA2SOMI	I/O	LVCMOS	DVCC	–
	S7	O	Analog	DVCC	–
56	P5.2	I/O	LVCMOS	DVCC	OFF
	UCA2CLK	I/O	LVCMOS	DVCC	–
	S6	O	Analog	DVCC	–
57	P5.3	I/O	LVCMOS	DVCC	OFF
	UCA2STE	I/O	LVCMOS	DVCC	–
	S5	O	Analog	DVCC	–
58	P5.4	I/O	LVCMOS	DVCC	OFF
	UCB1CLK	I/O	LVCMOS	DVCC	–
	S4	O	Analog	DVCC	–
59	P5.5	I/O	LVCMOS	DVCC	OFF
	TA0CLK	I	LVCMOS	DVCC	–
	UCB1SIMO	I/O	LVCMOS	DVCC	–
	UCB1SDA	I/O	LVCMOS	DVCC	–
	S3	O	Analog	DVCC	–
60	P5.6	I/O	LVCMOS	DVCC	OFF
	UCB1SOMI	I/O	LVCMOS	DVCC	–
	UCB1SCL	I/O	LVCMOS	DVCC	–
	S2	O	Analog	DVCC	–
61	P5.7	I/O	LVCMOS	DVCC	OFF
	UCB1STE	I/O	LVCMOS	DVCC	–
	S1	O	Analog	DVCC	–
62	P6.0	I/O	LVCMOS	DVCC	OFF
	COUT	I	LVCMOS	DVCC	–
	S0	O	Analog	DVCC	–
63	P6.4	I/O	LVCMOS	DVCC	OFF
63	COM0	O	Analog	DVCC	–
64	P6.5	I/O	LVCMOS	DVCC	OFF
64	COM1	O	Analog	DVCC	–
65	P6.6	I/O	LVCMOS	DVCC	OFF
	COM2	O	Analog	DVCC	–
	S38	O	Analog	DVCC	–
66	P6.7	I/O	LVCMOS	DVCC	OFF
	COM3	O	Analog	DVCC	–
	S37	O	Analog	DVCC	–
67	P7.0	I/O	LVCMOS	DVCC	OFF
	UCA2TXD	O	LVCMOS	DVCC	–
	UCA2SIMO	I/O	LVCMOS	DVCC	–
	ACLK	O	LVCMOS	DVCC	–
	COM4	O	Analog	DVCC	–
	S36	O	Analog	DVCC	–
68	P7.1	I/O	LVCMOS	DVCC	OFF
	UCA2RXD	I	LVCMOS	DVCC	–
	UCA2SOMI	I/O	LVCMOS	DVCC	–
	SMCLK	O	LVCMOS	DVCC	–
	COM5	O	Analog	DVCC	–
	S35	O	Analog	DVCC	–
69	P7.2	I/O	LVCMOS	DVCC	OFF
	UCA2CLK	I/O	LVCMOS	DVCC	–
	TB0.0	I/O	LVCMOS	DVCC	–
	COM6	O	Analog	DVCC	–
	S34	O	Analog	DVCC	–
70	P7.3	I/O	LVCMOS	DVCC	OFF
	UCA2STE	I/O	LVCMOS	DVCC	–
	TB0.1	I/O	LVCMOS	DVCC	–
	COM7	O	Analog	DVCC	–
	S33	O	Analog	DVCC	–
71	P6.1	I/O	LVCMOS	DVCC	OFF
71	R03	I/O	Analog	DVCC	–
72	P6.2	I/O	LVCMOS	DVCC	OFF
	R13	I/O	Analog	DVCC	–
	LCDREF	I	Analog	-	–
73	P6.3	I/O	LVCMOS	DVCC	OFF
73	R23	I/O	Analog	DVCC	–
74	R33	I/O	Analog	DVCC	-
74	LCDCAP	I/O	Analog	DVCC	–
75	DVSS3	P	Power	–	N/A
76	DVCC3	P	Power	–	N/A
77	P7.4	I/O	LVCMOS	DVCC	OFF
	TA0.1	I/O	LVCMOS	DVCC	–
	MTIF_OUT_IN	I/O	LVCMOS	DVCC	–
78	P7.5	I/O	LVCMOS	DVCC	OFF
	TA1.1	I/O	LVCMOS	DVCC	–
	MTIF_PIN_EN	I	LVCMOS	DVCC	–
79	P8.0	I/O	LVCMOS	DVCC	OFF
	UCA3STE	I/O	LVCMOS	DVCC	–
	TB0.2	I/O	LVCMOS	DVCC	–
	DMAE0	I	LVCMOS	DVCC	–
80	P8.1	I/O	LVCMOS	DVCC	OFF
	UCA3CLK	I/O	LVCMOS	DVCC	–
	TB0.3	I/O	LVCMOS	DVCC	–
	TB0OUTH	I	LVCMOS	DVCC	–
81	P8.2	I/O	LVCMOS	DVCC	OFF
	UCA3RXD	O	LVCMOS	DVCC	–
	UCA3SOMI	I/O	LVCMOS	DVCC	–
	MCLK	O	LVCMOS	DVCC	–
82	P8.3	I/O	LVCMOS	DVCC	OFF
	UCA3TXD	O	LVCMOS	DVCC	–
	UCA3SIMO	I/O	LVCMOS	DVCC	–
	RTCCLK	O	LVCMOS	DVCC	–
83	P7.6	I/O	LVCMOS	DVCC	OFF
	TA4.1	I/O	LVCMOS	DVCC	–
	DMAE0	I	LVCMOS	DVCC	–
	COUT	O	LVCMOS	DVCC	–
84	P7.7	I/O	LVCMOS	DVCC	OFF
	TA0.2	I/O	LVCMOS	DVCC	–
	TB0OUTH	I	LVCMOS	DVCC	–
	COUT	O	LVCMOS	DVCC	–
85	CH1_IN	I	Analog	PVCC	–
86	CH1_OUT	O	Analog	PVCC	–
87	PVSS	P	Power	–	N/A
88	PVCC	P	Power	–	N/A
89	PVSS	P	Power	–	N/A
90	CH0_OUT	O	Analog	PVCC	–
91	CH0_IN	I	Analog	PVCC	–
92	P8.4	I/O	LVCMOS	DVCC	OFF
	UCB1CLK	I/O	LVCMOS	DVCC	–
	TA1.2	I/O	LVCMOS	DVCC	–
	A10	I	Analog	DVCC	–
93	P8.5	I/O	LVCMOS	DVCC	OFF
	UCB1SIMO	I/O	LVCMOS	DVCC	–
	UCB1SDA	I/O	LVCMOS	DVCC	–
	A11	I	Analog	DVCC	–
94	P8.6	I/O	LVCMOS	DVCC	OFF
	UCB1SOMI	I/O	LVCMOS	DVCC	–
	UCB1SCL	I/O	LVCMOS	DVCC	–
	A12	I	Analog	DVCC	–
95	P8.7	I/O	LVCMOS	DVCC	OFF
	UCB1STE	I/O	LVCMOS	DVCC	–
	USSXT_BOUT	I/O	LVCMOS	DVCC	–
	A13	I	Analog	DVCC	–
96	AVSS5	P	Power	–	N/A
97	USSXTIN⁽⁶⁾	I	Analog	1.5V	–
98	USSXTOUT⁽⁶⁾	O	Analog	1.5V	–
99	AVSS1	P	Power	–	N/A
100	AVCC1	P	Power	–	N/A

(1) The signal that is listed first for each pin is the reset default pin name.

(2) Signal Types: I = Input, O = Output, I/O = Input or Output.

(3) Buffer Types: LVCMOS, Analog, or Power (see Table 7-3 for details)

(4) To determine the pin mux encodings for each pin, see Section 9.14.

(5) The power source shown in this table is the I/O power source, which may differ from the module power source.

(6) Do not connect USSXTIN and USSXTOUT pins to AVCC nor to DVCC. USSXTIN does not support bypass mode, so do not drive an external clock on the USSXTIN pin.

(7) Reset States:
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
PU = Pullup is enabled
PD = Pulldown is enabled
N/A = Not applicable