米6体育平台手机版

9.14.2 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger

Figure 9-3 shows the port diagram. Table 9-25 summarizes the selection of the pin function.

Functional representation only.

Figure 9-3 Port P1 (P1.0 to P1.1) Diagram

Table 9-25 Port P1 (P1.0 to P1.1) Pin Functions

PIN NAME (P1.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P1.x)	x	FUNCTION	P1DIR.x	P1SEL1.x	P1SEL0.x
P1.0/UCA1CLK/TA1.0/A0/C0/ VREF-/VeREF-	0	P1.0 (I/O)	0 = Input, 1 = Output	0	0
		UCA1CLK	X⁽⁴⁾	0	1
		TA1.CCI0A	0	1	0
		TA1.0	1	1	0
		A0, C0, VREF-, VeREF-⁽²⁾⁽³⁾	X	1	1
P1.1/UCA1STE/TA4.0/A1/C1/ VREF+/VeREF+	1	P1.1 (I/O)	0 = Input, 1 = Output	0	0
		UCA1STE	X⁽⁴⁾	0	1
		TA4.CCI0A	0	1	0
		TA4.0	1	1	0
		A1, C1, VREF+, VeREF+⁽²⁾⁽³⁾	X	1	1

(1) X = Don't care

(2) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

(3) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.

(4) Direction controlled by eUSCI_A1 module.