SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
This register is used to program the bit width and bit quantum. Values are programmed to the system clock frequency. This register is write-enabled by setting the CCE and INIT bits in the CANCTL register. See Section 11.3.15 for more information.
CANBIT is shown in Figure 11-8 and described in Table 11-11.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0x0 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TSEG2 | TSEG1 | SJW | BRP | |||||||||||
| R-0x0 | R/W-0x2 | R/W-0x3 | R/W-0x0 | R/W-0x1 | |||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-15 | RESERVED | R | 0x0 |
|
| 14-12 | TSEG2 | R/W | 0x2 |
Time Segment after Sample Point. 0x00 to 0x07: The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. So, for example, the reset value of 0x2 means that 3 (2+1) bit time quanta are defined for Phase2 (see Figure 11-4). The bit time quanta is defined by the BRP field. |
| 11-8 | TSEG1 | R/W | 0x3 |
Time Segment Before Sample Point. 0x00 to 0x0F: The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. So, for example, the reset value of 0x3 means that 4 (3+1) bit time quanta are defined for Phase1 (see Figure 11-4). The bit time quanta is defined by the BRP field. |
| 7-6 | SJW | R/W | 0x0 |
(Re)Synchronization Jump Width. 0x00 to 0x03: The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. During the start of frame (SOF), if the CAN controller detects a phase error (misalignment), it can adjust the length of TSEG2 or TSEG1 by the value in SJW. So the reset value of 0 adjusts the length by 1 bit time quanta. |
| 5-0 | BRP | R/W | 0x1 |
Baud Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quantum. 0x00 to 0x03F: The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. BRP defines the number of CAN clock periods that make up 1 bit time quanta, so the reset value is 2 bit time quanta (1+1). The CANBRPE register can be used to further divide the bit time. |