SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 11-6 lists the memory-mapped registers for the CAN. All register offset addresses not listed in Table 11-6 should be considered as RESERVED locations and the register contents should not be modified.
All address offsets are relative to the base address of the CAN module:
The CAN controller clock must be enabled before the registers can be programmed. There must be a delay of 3 system clock cycles after the CAN module clock is enabled before any CAN module registers are accessed.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | CANCTL | CAN Control | Section 11.4.1 |
| 0x4 | CANSTS | CAN Status | Section 11.4.2 |
| 0x8 | CANERR | CAN Error Counter | Section 11.4.3 |
| 0xC | CANBIT | CAN Bit Timing | Section 11.4.4 |
| 0x10 | CANINT | CAN Interrupt | Section 11.4.5 |
| 0x14 | CANTST | CAN Test | Section 11.4.6 |
| 0x18 | CANBRPE | CAN Baud Rate Prescaler Extension | Section 11.4.7 |
| 0x20 | CANIF1CRQ | CAN IF1 Command Request | Section 11.4.8 |
| 0x24 | CANIF1CMSK | CAN IF1 Command Mask | Section 11.4.9 |
| 0x28 | CANIF1MSK1 | CAN IF1 Mask 1 | Section 11.4.10 |
| 0x2C | CANIF1MSK2 | CAN IF1 Mask 2 | Section 11.4.11 |
| 0x30 | CANIF1ARB1 | CAN IF1 Arbitration 1 | Section 11.4.12 |
| 0x34 | CANIF1ARB2 | CAN IF1 Arbitration 2 | Section 11.4.13 |
| 0x38 | CANIF1MCTL | CAN IF1 Message Control | Section 11.4.14 |
| 0x3C | CANIF1DA1 | CAN IF1 Data A1 | Section 11.4.15 |
| 0x40 | CANIF1DA2 | CAN IF1 Data A2 | Section 11.4.15 |
| 0x44 | CANIF1DB1 | CAN IF1 Data B1 | Section 11.4.15 |
| 0x48 | CANIF1DB2 | CAN IF1 Data B2 | Section 11.4.15 |
| 0x80 | CANIF2CRQ | CAN IF2 Command Request | Section 11.4.8 |
| 0x84 | CANIF2CMSK | CAN IF2 Command Mask | Section 11.4.9 |
| 0x88 | CANIF2MSK1 | CAN IF2 Mask 1 | Section 11.4.10 |
| 0x8C | CANIF2MSK2 | CAN IF2 Mask 2 | Section 11.4.11 |
| 0x90 | CANIF2ARB1 | CAN IF2 Arbitration 1 | Section 11.4.12 |
| 0x94 | CANIF2ARB2 | CAN IF2 Arbitration 2 | Section 11.4.13 |
| 0x98 | CANIF2MCTL | CAN IF2 Message Control | Section 11.4.14 |
| 0x9C | CANIF2DA1 | CAN IF2 Data A1 | Section 11.4.15 |
| 0xA0 | CANIF2DA2 | CAN IF2 Data A2 | Section 11.4.15 |
| 0xA4 | CANIF2DB1 | CAN IF2 Data B1 | Section 11.4.15 |
| 0xA8 | CANIF2DB2 | CAN IF2 Data B2 | Section 11.4.15 |
| 0x100 | CANTXRQ1 | CAN Transmission Request 1 | Section 11.4.16 |
| 0x104 | CANTXRQ2 | CAN Transmission Request 2 | Section 11.4.16 |
| 0x120 | CANNWDA1 | CAN New Data 1 | Section 11.4.17 |
| 0x124 | CANNWDA2 | CAN New Data 2 | Section 11.4.17 |
| 0x140 | CANMSG1INT | CAN Message 1 Interrupt Pending | Section 11.4.18 |
| 0x144 | CANMSG2INT | CAN Message 2 Interrupt Pending | Section 11.4.18 |
| 0x160 | CANMSG1VAL | CAN Message 1 Valid | Section 11.4.19 |
| 0x164 | CANMSG2VAL | CAN Message 2 Valid | Section 11.4.19 |
Complex bit access types are encoded to fit into small table cells. Table 11-7 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |