| 31-8 |
RESERVED |
R |
0x0 |
|
| 7 |
WRNRD |
R/W |
0x0 |
Write, Not Read. Interrupt pending and new data conditions in the message buffer can be cleared by reading from the buffer (WRNRD = 0) when the CLRINTPND or NEWDAT bits are set.
0x0 = Transfer the data in the CAN message object specified by the MNUM field in the CANIFnCRQ register into the CANIFn registers.
0x1 = Transfer the data in the CANIFn registers to the CAN message object specified by the MNUM field in the CAN Command Request (CANIFnCRQ).
|
| 6 |
MASK |
R/W |
0x0 |
Access Mask Bits.
0x0 = Mask bits unchanged.
0x1 = Transfer IDMASK + DIR + MXTD of the message object into the Interface registers.
|
| 5 |
ARB |
R/W |
0x0 |
Access Arbitration Bits.
0x0 = Arbitration bits unchanged.
0x1 = Transfer ID + DIR + XTD + MSGVAL of the message object into the Interface registers.
|
| 4 |
CONTROL |
R/W |
0x0 |
Access Control Bits.
0x0 = Control bits unchanged.
0x1 = Transfer control bits from the CANIFnMCTL register into the Interface registers.
|
| 3 |
CLRINTPND |
R/W |
0x0 |
Clear Interrupt Pending Bit. The function of this bit depends on the configuration of the WRNRD bit.
0x0 = If WRNRD is clear, the interrupt pending status is transferred from the message buffer into the CANIFnMCTL register.If WRNRD is set, the INTPND bit in the message object remains unchanged.
0x1 = If WRNRD is clear, the interrupt pending status is cleared in the message buffer. Note the value of this bit that is transferred to the CANIFnMCTL register always reflects the status of the bits before clearing.If WRNRD is set, the INTPND bit is cleared in the message object.
|
| 2 |
NEWDAT / TXRQST |
R/W |
0x0 |
NEWDAT / TXRQST Bit. The function of this bit depends on the configuration of the WRNRD bit.
0x0 = If WRNRD is clear, the value of the new data status is transferred from the message buffer into the CANIFnMCTL register.If WRNRD is set, a transmission is not requested.
0x1 = If WRNRD is clear, the new data status is cleared in the message buffer. Note the value of this bit that is transferred to the CANIFnMCTL register always reflects the status of the bits before clearing.If WRNRD is set, a transmission is requested. Note that when this bit is set, the TXRQST bit in the CANIFnMCTL register is ignored.
|
| 1 |
DATAA |
R/W |
0x0 |
Access Data Byte 0 to 3. The function of this bit depends on the configuration of the WRNRD bit.
0x0 = Data bytes 0 to 3 are unchanged.
0x1 = If WRNRD is clear, transfer data bytes 0 to 3 in CANIFnDA1 and CANIFnDA2 to the message object.If WRNRD is set, transfer data bytes 0 to 3 in message object to CANIFnDA1 and CANIFnDA2.
|
| 0 |
DATAB |
R/W |
0x0 |
Access Data Byte 4 to 7. The function of this bit depends on the configuration of the WRNRD bit as follows:
0x0 = Data bytes 4 to 7 are unchanged.
0x1 = If WRNRD is clear, transfer data bytes 4 to 7 in CANIFnDA1 and CANIFnDA2 to the message object.If WRNRD is set, transfer data bytes 4 to 7 in message object to CANIFnDA1 and CANIFnDA2.
|