SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
CAN IF1 Command Request (CANIF1CRQ), offset 0x020
CAN IF2 Command Request (CANIF2CRQ), offset 0x080
A message transfer is started as soon as there is a write of the message object number to the MNUM field when the TXRQST bit in the CANIF1MCTL register is set. With this write operation, the BUSY bit is automatically set to indicate that a transfer between the CAN Interface Registers and the internal message RAM is in progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer between the interface register and the message RAM completes, which then clears the BUSY bit.
CANIFnCRQ is shown in Figure 11-12 and described in Table 11-15.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BUSY | RESERVED | ||||||
R-0x0 | R-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MNUM | ||||||
R-0x0 | R/W-0x1 | ||||||